Information and Systems-Neurocomputing(Date:2006/11/04)

Presentation
表紙

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[Date]2006/11/4
[Paper #]
目次

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[Date]2006/11/4
[Paper #]
Investigation of a Switched-Resistor Network to Develop a Silicon Retina

Seiji KAMEDA,  Shosuke MORIMOTO,  Atsushi IWATA,  

[Date]2006/11/4
[Paper #]NC2006-63
A Pulse-type Hardware Model of an Input Region in a Visual Cortex

Takaaki IWAMOTO,  Yoshifumi SEKINE,  

[Date]2006/11/4
[Paper #]NC2006-64
A VLSI-IMPLEMENTATION-FRIENDLY EGO-MOTION DETECTION ALGORITHM BASED ON EDGE-HISTOGRAM MATCHING

Jia HAO,  Tadashi SHIBATA,  

[Date]2006/11/4
[Paper #]NC2006-65
A K-means VLSI Processor and its Application to Autonomous Area Segmentation in Images

Shigetaka MORIKAWA,  Kiyoto ITO,  Tadashi SHIBATA,  

[Date]2006/11/4
[Paper #]NC2006-66
A VLSI brain processor system mimicking the processing in mind : Building real-time visual perception systems

Tadashi Shibata,  

[Date]2006/11/4
[Paper #]NC2006-67
Bifurcation phenomena of artificial neuron model with piecewise linear base signal

Toshimitsu OHTANI,  Toshimichi SAITO,  Hiroyuki TORIKAI,  

[Date]2006/11/4
[Paper #]NC2006-68
An approach toward learning algorithm for Digital Spiking Neuron

Hiroyuki TORIKAI,  Toshimichi SAITO,  

[Date]2006/11/4
[Paper #]NC2006-69
Four Valued T-Gate with neuron MOSFETs

Yoshikazu ISHIMARU,  Hiroyasu KONDO,  Yohei ISHIKAWA,  Sumio FUKAI,  

[Date]2006/11/4
[Paper #]NC2006-70
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[Date]2006/11/4
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[Date]2006/11/4
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[Date]2006/11/4
[Paper #]