Information and Systems-Image Engineering(Date:2022/11/28)

Presentation
A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage

Ruoxi Yu(Chiba Univ.),  Kazuteru Namba(Chiba Univ.),  

[Date]2022-11-28
[Paper #]VLD2022-24,ICD2022-41,DC2022-40,RECONF2022-47
A Routing Method by SAT for Set-Pair Routing Problem

Koki Nagakura(Tokyo Univ of A and T),  Rintaro Yokoya(Tokyo Univ of A and T),  Kunihiro Fujiyoshi(Tokyo Univ of A and T),  

[Date]2022-11-28
[Paper #]VLD2022-21,ICD2022-38,DC2022-37,RECONF2022-44
On reduction of test patterns for a Multiplier Using Approximate Computing

Shogo Tokai(Tokushima Univ),  Daichi Akamatsu(Tokushima Univ),  Hiroyuki Yotsuyanagi(Tokushima Univ),  Masaki Hashizume(Tokushima Univ),  

[Date]2022-11-28
[Paper #]VLD2022-23,ICD2022-40,DC2022-39,RECONF2022-46
A Study of a Design Methodology for Various CGRA based on Diplomacy

Takuya Kojima(UTokyo/JST PRESTO),  Makoto Saito(UTokyo),  Hiroshi Nakamura(UTokyo),  

[Date]2022-11-28
[Paper #]VLD2022-22,ICD2022-39,DC2022-38,RECONF2022-45
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM

Masashi Imai(Hirosaki Univ.),  Kenji Kise(Tokyo Tech.),  Tomohiro Yoneda(NII),  

[Date]2022-11-28
[Paper #]VLD2022-19,ICD2022-36,DC2022-35,RECONF2022-42
A Study on Co-Optimization of logical structure and bit-line placement for Parallel Prefix Adders

Mineo Kaneko(JAIST),  

[Date]2022-11-28
[Paper #]VLD2022-20,ICD2022-37,DC2022-36,RECONF2022-43
FPGA-based Accelerators System with Autonomous DMA Engine

Tomoya Yokono(NTT),  Yoshiro Yamabe(NTT),  Kenji Tanaka(NTT),  Yuki Arikawa(NTT),  Teruaki Ishizaki(NTT),  

[Date]2022-11-29
[Paper #]VLD2022-28,ICD2022-45,DC2022-44,RECONF2022-51
NA

Tomokazu Yoshimura(Waseda Univ.),  Shirai Tatsuhiko(Waseda Univ.),  Masashi Tawada(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-34,ICD2022-51,DC2022-50,RECONF2022-57
Test Generation Merhod based on RTL Design for Diagnosability

Yuya Chida(Nihon univ.),  Toshinori Hosokawa(Nihon univ.),  Koji Yamazaki(Meiji Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-26,ICD2022-43,DC2022-42,RECONF2022-49
Method of Halved Interaction Elements with Regularity Arrangement that achieves Independent Double Systems for Scalable Fully Coupled Annealing Processing

Shinjiro Kitahara(TUS),  Akari Endo(TUS),  Taichi Megumi(TUS),  Takayuki Kawahara(TUS),  

[Date]2022-11-29
[Paper #]VLD2022-31,ICD2022-48,DC2022-47,RECONF2022-54
N/A

Soma Kawakami(Waseda Univ.),  Dema Ba(NTT),  Kentaro Ohno(NTT),  Satoshi Yagi(NTT),  Junji Teramoto(NTT),  Nozomu Togawa(Waseda Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-35,ICD2022-52,DC2022-51,RECONF2022-58
A Don't Care Filling Method of control signals for controllers to Maximize the Number of Distinguishable Hard ware Element Pairs

Yui Otsuka(Nihon Univ.),  Yuya Chida(Nihon Univ.),  Xu Haofeng(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Kouji Yamazaki(Meiji Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-25,ICD2022-42,DC2022-41,RECONF2022-48
Evaluating system level security of cryptography module

Takumi Matsumaru(Kobe Univ.),  Kazuki Monta(Kobe Univ.),  Takaaki Okidono(SCU),  Takuji Miki(Kobe Univ.),  Makoto Nagata(Kobe Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-32,ICD2022-49,DC2022-48,RECONF2022-55
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test

Rei Miura(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Masayoshi Yoshimura(Kyoto Sangyou Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-27,ICD2022-44,DC2022-43,RECONF2022-50
Evaluation of power delivery networks in secure semiconductor systems

Masaru Mashiba(Kobe Univ.),  Kazuki Monta(Kobe Univ.),  Takaaki Okidono(SCU),  Takuzi Miki(Kobe Univ.),  Makoto Nagata(Kobe Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-33,ICD2022-50,DC2022-49,RECONF2022-56
A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems

Kazuei Hironaka(Keio Univ.),  Kensuke Iizuka(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-29,ICD2022-46,DC2022-45,RECONF2022-52
N/A

Yuta Yachi(Waseda Univ.),  Masashi Tawada(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-37,ICD2022-54,DC2022-53,RECONF2022-60
N/A

Keisuke Fukada(Waseda Univ.),  Matthieu Parizy(Waseda Univ./Fujitsu LTD.),  Yoshinori Tomita(Fujitsu LTD.),  Nozomu Togawa(Waseda Univ.),  

[Date]2022-11-29
[Paper #]VLD2022-36,ICD2022-53,DC2022-52,RECONF2022-59
マルチFPGAシステムの高位合成シミュレーション手法に関する検討

Haruto Ikehara(Nagasaki Univ.),  Keigo Motoyoshi(Nagasaki Univ.),  Koki Fukuda(Nagasaki Univ.),  Taito Manabe(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Tomohiro Ueno(Riken),  Kentaro Sano(Riken),  

[Date]2022-11-29
[Paper #]VLD2022-30,ICD2022-47,DC2022-46,RECONF2022-53
Design and Trial Production of Stochastic Resonance Processor using Differential Input Buffer in FPGA

Akihiko Tsukahara(Tokyo Denki Univ.),  Sung-Gwi Cho(Tokyo Denki Univ.),  Keita Tanaka(Tokyo Denki Univ.),  Akihiko Homma(Tokyo Denki Univ.),  Yoshinori Uchikawa(Tokyo Denki Univ.),  

[Date]2022-11-30
[Paper #]VLD2022-49,ICD2022-66,DC2022-65,RECONF2022-72
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