IEICE Technical Committee

Information and Systems-Image Engineering(Date:2022/06/07)

Presentation

Hardware implementation of the protocol for ROS2 and robot modules without CPU

Daiki Matsunaga(AXE), Tomoya Shoji(AXE), Shozo Takeoka(AXE),

[Date]2022-06-07
[Paper #]RECONF2022-3

Development of Vehicles GPS Time Synchronized Vibration Measurement System for Bridge Health Monitoring

Masaaki Ono(Univ. of Tsukuba), Ryota Shin(Univ. of Tsukuba), Yukihiko Okada(Univ. of Tsukuba), Ryosuke Yamamoto(Univ. of Tsukuba),

[Date]2022-06-07
[Paper #]RECONF2022-12

Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER

Rintaro Sakai(Kumamoto Univ. /R-CSS), Yasuhiro Nakahara(Kumamoto Univ. /R-CSS), Kentaro Sano(R-CCS), Masahiro Iida(Kumamoto Univ. /R-CSS),

[Date]2022-06-07
[Paper #]RECONF2022-11

精度保証付き高速モデル予測制御の固定小数点実装に向けた検討

Shoin Maeda(UT), Hiroshi Nakamura(UT), Hideki Takase(UT),

[Date]2022-06-07
[Paper #]RECONF2022-2

Optically reconfigurable gate array VLSI with a perfect parallel configuration function

Sae Goto(Okayama Univ.), Minoru Watanabe(Okayama Univ.), Nobuya Watanabe(Okayama Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-6

290 Mrad total-ionizing-dose tolerance experiment for an optically reconfigurable gate array VLSI

Kaho Yamada(Okayama Univ.), Takeshi Okazaki(Okayama Univ.), Minoru Watanabe(Okayama Univ.), Nobuya Watanabe(Okayama Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-7

Design of a Quantum Annealing Accelerator for Sparse Ising Model

Yuta Ohma(Tohoku Univ.), Hasitha Muthumala Waidyasooriya(Tohoku Univ.), Masanori Hariyama(Tohoku Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-10

An Implementation of a Pattern-matching Accelerator on a RISC-V Processor

Riku Takayama(Yamagata Univ.), Jubee Tada(Yamagata Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-9

高位合成によるマルチバンクメモリの記述方法の検討

Kazuya Tanigawa(HCU),

[Date]2022-06-07
[Paper #]RECONF2022-8

Vector Register Sharing Mechanism for Hardware Acceleration

Tomoaki Tanaka(TUAT), Ryousuke Higashi(TUAT), Kiyofumi Tanaka(JAIST), Yasunori Osana(Univ. of the Ryukyus), Takefumi Miyoshi(Wasalabo), Jubee Tada(Yamagata Univ.), Hironori Nakajo(TUAT),

[Date]2022-06-07
[Paper #]RECONF2022-5

Accelerating Deep Learning-based Path Planning Method on FPGAs

Keisuke Sugiura(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-1

Performance Evaluation of Fault-Tolerant Routing Methods Using NAS Parallel Benchmarks

Yota Kurokawa(Yamaguchi Univ.), Masaru Fukushi(Yamaguchi Univ.),

[Date]2022-06-07
[Paper #]RECONF2022-4

Regularization based CNN Optimizing and the acceleration on FPGA

Hengyi Li(RU), Xuebin Yue(RU), Lin Meng(RU),

[Date]2022-06-08
[Paper #]RECONF2022-20

A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration

Li Qi(Ritsumeikan Univ.), Li Hengyi(Ritsumeikan Univ.), Meng Lin(Ritsumeikan Univ.),

[Date]2022-06-08
[Paper #]RECONF2022-21

GPU-FPGAの直接データ転送方式の検討

Shun Kasai(Ryukyu Univ.), Yasunori Osana(Ryukyu Univ.),

[Date]2022-06-08
[Paper #]RECONF2022-16

Investigation of methods to accelerate inference processing by deep learning

Seiya Iwamoto(OIT), Chikako Nakanishi(OIT),

[Date]2022-06-08
[Paper #]RECONF2022-13

Consideration of speeding up AI inference processing by cooperative operation of hardware and software

Tomoya Kawakami(OIT), Chikako Nakanishi(OIT),

[Date]2022-06-08
[Paper #]RECONF2022-14

FPGAによるHDR合成処理への画像圧縮技術の適用

Masahiro Nishimura(Nagasaki Univ.), Yuta Imamura(Nagasaki Univ.), Taito Manabe(Nagasaki Univ.), Yuichiro Shibata(Nagasaki Univ.),

[Date]2022-06-08
[Paper #]RECONF2022-24

Helmholtzの原理に基づく曲線輪郭線検出のFPGA実装

Shintaro Matsui(Nagasaki Univ.), Taito Manabe(Nagasaki Univ.), Yuichiro Shibata(Nagasaki Univ.),

[Date]2022-06-08
[Paper #]RECONF2022-25

Structural Sparsification of Activations and Weights for Low Latency Implementation of CNN

Akira Jinguji(Tokyo Tech), Naoto Soga(Tokyo Tech), Hiroki Nakahara(Tokyo Tech),

[Date]2022-06-08
[Paper #]RECONF2022-22