Information and Systems-Image Engineering(Date:2021/07/20)

Presentation
Prototype Implementation of Non-Volatile Memory Support for RISC-V Keystone Enclave

Lena Yu(Waseda Univ.),  Yu Omori(Waseda Univ.),  Keiji Kimura(Waseda Univ.),  

[Date]2021-07-20
[Paper #]CPSY2021-2,DC2021-2
ルーティングの動的再構成によるネットワークのデッドロックフリー性・低遅延性の両立

Ryuta Kawano(JAIST),  Hiroki Matsutani(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2021-07-20
[Paper #]CPSY2021-5,DC2021-5
Content addressable memory using multi-level cell phase-change memory

Tomohiro Takahashi(Chiba Univ.),  Kazuteru Namba(Chiba Univ.),  

[Date]2021-07-20
[Paper #]CPSY2021-1,DC2021-1
PYNQクラスタの評価

Hideharu Amano(Keio Univ.),  Takumi Inage(Keio Univ.),  Kouhei Ito(Keio Univ.),  Yasuyu Fukusihma(Keio Univ.),  Kensuke Iizuka(Keio Univ.),  Kazuei Hironaka(Keio Univ.),  

[Date]2021-07-20
[Paper #]CPSY2021-3,DC2021-3
A study of inter-node communication on a tightly coupled FPGA cluster

Ryohei Niwase(Univ. of Tsukuba),  Hikaru Harasawa(Univ. of Tsukuba),  Fan Ruochong(Univ. of Tsukuba),  Yoshiki Yamaguchi(Univ. of Tsukuba),  Taisuke Boku(Univ. of Tsukuba),  

[Date]2021-07-20
[Paper #]CPSY2021-4,DC2021-4
A Domain Adaptation Method using Light-Weight Neural ODE for Low-Cost FPGAs

Hiroki Kawakami(Keio Univ.),  Hirohisa Watanabe(Keio Univ.),  Keisuke Sugiura(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2021-07-21
[Paper #]CPSY2021-10,DC2021-10
A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning

Masaki Furukawa(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2021-07-21
[Paper #]CPSY2021-6,DC2021-6
Development of Spiking Neural Network Using Mem Capacitor

Atsushi Sawada(NAIST),  Reon Oshio(NAIST),  Takeshi Nomura(NAIST),  Renyuan Zhang(NAIST),  Mutsumi Kimura(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2021-07-21
[Paper #]CPSY2021-11,DC2021-11
シストリックアレイ向け確率的コンピューティングの予備評価

Tomoya Akabe(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2021-07-21
[Paper #]CPSY2021-9,DC2021-9
Lossy Error Correction Coding for Vector-Matrix Multiplication

Leo Otani(Tokyo Tech),  Haruhiko Kaneko(Tokyo Tech),  

[Date]2021-07-21
[Paper #]CPSY2021-7,DC2021-7
FPGA向け浮動小数点数型ソーティングライブラリの提案と実装

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[Date]2021-07-21
[Paper #]CPSY2021-8,DC2021-8