Information and Systems-Image Engineering(Date:2021/06/08)

Presentation
Development of a simulator to explore the accelerator architecture for breadth-first search.

Yushi Haraguchi(HCU),  Kazuya Tanigawa(HCU),  Takaaki Miyajima(RIKEN),  Jens Huthmann(RIKEN),  Kentarou Sano(RIKEN),  Tetsuo Hironaka(HCU),  

[Date]2021-06-08
[Paper #]RECONF2021-3
乱数生成ノードの並列閾値最適化に基づくエッジ指向決定木アンサンブル学習

Shungo Kumazawa(Tokyo Tech),  Kazushi Kawamura(Tokyo Tech),  Thiem Van Chu(Tokyo Tech),  Masato Motomura(Tokyo Tech),  Jaehoon Yu(Tokyo Tech),  

[Date]2021-06-08
[Paper #]RECONF2021-2
Automatic generation of executable code for ReNA

Yuta Masuda(Kumamoto Univ.),  Yasuhiro Nakahara(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  

[Date]2021-06-08
[Paper #]RECONF2021-6
対称的二進表現に基づくビットスケーラブルCNN推論手法

Junnosuke Suzuki(Tokyo Tech),  Kota Ando(Tokyo Tech),  Kazutoshi Hirose(Tokyo Tech),  Kazushi Kawamura(Tokyo Tech),  Thiem Van Chu(Tokyo Tech),  Masato Motomura(Tokyo Tech),  yu jaehoon(Tokyo Tech),  

[Date]2021-06-08
[Paper #]RECONF2021-7
A Case for FPGA Implementation of Deep Neural Network Based 2D Point Cloud Registration

Keisuke Sugiura(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2021-06-08
[Paper #]RECONF2021-5
特徴空間事前分割に基づく決定木アンサンブルのFPGA推論アクセラレータ

Ryuichi Kitajima(Tokyo Tech),  Kazushi Kawamura(Tokyo Tech),  Jaehoon Yu(Tokyo Tech),  Masato Motomura(Tokyo Tech),  Thiem Van Chu(Tokyo Tech),  

[Date]2021-06-08
[Paper #]RECONF2021-4
[Invited Talk] Basics, Applications, and International Standardization of Physically Unclonable Functions (PUFs)

Yohei Hori(AIST),  

[Date]2021-06-08
[Paper #]RECONF2021-1
コンパクション処理を活用した正規パス問合わせアクセラレータのFPGA実装

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[Date]2021-06-09
[Paper #]RECONF2021-12
Size-independent high-speed FPGA implementation of Gaussian-Jordan method using recursive function calls with C++ templates

Yuuki Katsusaka(Hiroshima City Univ.),  Atsushi Kubota(Hiroshima City Univ.),  Tetsuo Hironaka(Hiroshima City Univ.),  

[Date]2021-06-09
[Paper #]
A 64-bit RISC-V many-core architecture on FPGAs

Qixiang Gao(Univ. of Tsukuba),  Yoshiki Yamaguchi(Univ. of Tsukuba),  

[Date]2021-06-09
[Paper #]RECONF2021-16
Development of the SYCL interface for FPGA clusters and evaluation of CPU-FPGA collaboration

Satoshi Kaneko(Tohoku Univ.),  Hiroyuki Takizawa(Tohoku Univ.),  Kentaro Sano(RIKEN),  

[Date]2021-06-09
[Paper #]RECONF2021-15
大規模FPGAクラスタのための再構成可能な仮想回線交換網

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[Date]2021-06-09
[Paper #]RECONF2021-14
FPGAを用いたフルパイプラインによるバイラテラルフィルタの高速化手法

Nobuho Hashimoto(The Univ. of Tokyo),  Shinya Takamaeda(The Univ. of Tokyo),  

[Date]2021-06-09
[Paper #]RECONF2021-8
An implementation of a satisfiability problem solver : Amoeba SAT on M-KUBOS board

Yan Ying Jie(Keio Univ.),  Masashi Aono(Keio Univ.),  Hideharu Amano(Keio Univ.),  Kaori Ohkoda(Amoeba Energy),  Shingo Fukuda(Amoeba Energy),  Saito Kenta(Amoeba Energy),  Seiya Kasai(Hokkaido Univ.),  

[Date]2021-06-09
[Paper #]RECONF2021-13
FPGA Implementation of Real-Time Video Compression Based on Adaptive Differential Coding

Taito Manabe(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  

[Date]2021-06-09
[Paper #]RECONF2021-9
FPGAによるハイダイナミックレンジ合成処理への拡張畳み込みの適用

Taichi Katayama(Nagasaki Univ.),  Yuta Imamura(Nagasaki Univ.),  Taito Manabe(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  

[Date]2021-06-09
[Paper #]RECONF2021-10
[Invited Talk] Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation

Kosuke Tatsumura(TOSHIBA),  

[Date]2021-06-09
[Paper #]RECONF2021-11