Information and Systems-Image Engineering(Date:2020/02/26)

Presentation
A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs

Yuki Takeuchi(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Hiroshi Yamazaki(Nihon Univ.),  Masayoshi Yoshimura(Kyoto Sangyo Univ.),  

[Date]2020-02-26
[Paper #]DC2019-90
A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT

Kenichiro Misawa(Nihon Univ),  Toshinori Hosokawa(Nihon Univ),  Hiroshi Yamazaki(Nihon Univ),  Masayoshi Yoshimura(Kyouto Sangyo Univ),  Masayuki Arai(Nihon Univ),  

[Date]2020-02-26
[Paper #]DC2019-92
On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor

Masayuki Gondo(Kyutech),  Yousuke Miyake(Kyutech),  Seiji Kajihara(Kyutech),  

[Date]2020-02-26
[Paper #]DC2019-86
Soft Error Tolerance of Power-Supply-Noise Hardened Latches

Yuya Kinoshita(Tokyo Metropolitan Univ.),  Yukiya Miura(Tokyo Metropolitan Univ.),  

[Date]2020-02-26
[Paper #]DC2019-97
Frequency Variation of Ring Oscillators During Long-Time Operation on FPGA

Shingo Tsutsumi(Tokyo Metropolitan Univ.),  Yukiya Miura(Tokyo Metropolitan Univ.),  

[Date]2020-02-26
[Paper #]DC2019-95
Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing

Tomoki Aono(Ehime Univ.),  Norihiro Nakaoka(Ehime Univ.),  Shyu Saikou(Ehime Univ.),  Wang Senling(Ehime Univ.),  Higami Yoshinobu(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  Hiroyuki Iwata(Renesas),  Youichi Maeda(Renesas),  Jun Matsushima(Renesas),  

[Date]2020-02-26
[Paper #]DC2019-89
Glitch PUF utilizing Unrolled Architecture and its Evaluation

Yusuke Nozaki(Meijo Univ.),  Masaya Yoshikawa(Meijo Univ.),  

[Date]2020-02-26
[Paper #]DC2019-91
Defective Chip Prediction Modeling Using Convolutional Neural Networks

Ryunosuke Oka(Oita Univ.),  Satoshi Ohtake(Oita Univ.),  Kouichi Kumaki(Renesas),  

[Date]2020-02-26
[Paper #]DC2019-87
Power Analysis for Logic Area of LSI Including Memory Area

Yuya Kodama(Kyutech),  Kohei Miyase(Kyutech),  Daiki Takafuji(Kyutech),  Xiaoqing Wen(Kyutech),  Seiji Kajihara(Kyutech),  

[Date]2020-02-26
[Paper #]DC2019-93
Improving Controllability of Signal Transitions in the High Switching Area of LSI

Jie Shi(Kyutech),  Kohei Miyase(Kyutech),  Xiaoqing Wen(Kyutech),  Seiji Kajihara(Kyutech),  

[Date]2020-02-26
[Paper #]DC2019-94
Accurate Recycled FPGA Detection Based on Exhaustive Path Analysis

Michihiro Shintani(NAIST),  Foisal Ahmed(NAIST),  Michiko Inoue(NAIST),  

[Date]2020-02-26
[Paper #]DC2019-96
A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection

Ryotaroh Nakanishi(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  

[Date]2020-02-26
[Paper #]DC2019-88