Information and Systems-Image Engineering(Date:2019/05/09)

Presentation
Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory.

Fumiya Suzuki(Shonan Inst. of Tech.),  Shigeyoshi Watanabe(Shonan Inst. of Tech.),  

[Date]2019-05-09
[Paper #]RECONF2019-4
Efficient Instruction Fetch Architectures for a RISC-V Soft Processor

Hiromu Miyazaki(Tokyo Tech),  Junya Miura(Tokyo Tech),  Kenji Kise(Tokyo Tech),  

[Date]2019-05-09
[Paper #]RECONF2019-1
メモリ利用効率の良い自己動的再構成機構の検討

Shota Fukui(Nagasaki Univ.),  Yuichi Kawamata(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  

[Date]2019-05-09
[Paper #]RECONF2019-5
ステンシル計算を対象としたメモリアクセスを最適化するラインバッファ自動挿入手法の検討

Kazuya Tanigawa(HCU),  Daichi Ishizaki(HCU),  Atsushi Kubota(HCU),  Tetsuo Hironaka(HCU),  

[Date]2019-05-09
[Paper #]RECONF2019-3
A CNN-based Classifier for a Digital Spectrometer on a Radio Telescope

Hiroki Nakahara(Titech),  Shimpei Sato(Titech),  

[Date]2019-05-09
[Paper #]RECONF2019-19
A case study of an FPGA implementation for streaming data filtering

Hiroki Nakagawa(Kumamoto Univ.),  Yasutaka TsuTsumi(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2019-05-09
[Paper #]RECONF2019-8
[Invited Talk] Engineers' and Scientists' Way of Life

Kazuyuki Shudo(Tokyo Tech),  

[Date]2019-05-09
[Paper #]RECONF2019-9
RDMAを用いた密結合FPGAクラスタのメモリ間通信性能

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[Date]2019-05-09
[Paper #]RECONF2019-2
関数型言語Elixirを設計言語とするハードウェア設計環境の構想

Hideki Takase(Kyoto Univ./JST),  Kentaro Matsui(Kyoto Univ.),  Yoshihiro Ueno(Delight Systems),  Masakazu Mori(karabiner.inc),  Susumu Yamazaki(Univ. of Kitakyushu),  

[Date]2019-05-09
[Paper #]RECONF2019-7
High Level Synthesis of Recursive Description in a CPU+FPGA Co-design framework based on Ruby

Ryota Yamashita(TUAT),  Daichi Teruya(TUAT),  Hironori Nakajo(TUAT),  

[Date]2019-05-09
[Paper #]RECONF2019-6
Deep Learning Framework with Numerical Precision

Masato Kiyama(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  

[Date]2019-05-10
[Paper #]RECONF2019-15
パイプライン型Wave-Front-FetchグラフカットシステムのFPGA実装

Naofumi Yoshinaga(Nagasaki Univ.),  Ryo Kamasaka(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kiyoshi Oguri(Nagasaki Univ.),  

[Date]2019-05-10
[Paper #]RECONF2019-17
An FPGA Implementation of the Semantic Segmentation Model with Multi-path Structure

Youki Sada(titech),  Masayuki Shimoda(titech),  Shimpei Sato(titech),  Hiroki Nakahara(titech),  

[Date]2019-05-10
[Paper #]RECONF2019-10
Spatial-Separable Convolution: Low memory CNN for FPGA

Akira Jinguji(titech),  Masayuki Shimoda(titech),  Hiroki Nakahara(titech),  

[Date]2019-05-10
[Paper #]RECONF2019-16
Dither NN: 画像処理から着想を得た組込み向け量子化ニューラルネットワークの精度向上手法

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[Date]2019-05-10
[Paper #]RECONF2019-14
hoge

Kodai Ueyoshi(Hokkaido Univ.),  Taiga Ikeda(Hokkaido Univ.),  Kota Ando(Hokkaido Univ.),  Kazutoshi Hirose(Hokkaido Univ.),  Tetsuya Asai(Hokkaido Univ.),  Shinya Takamaeda-Yamazaki(Hokkaido Univ.),  Masato Motomura(Tokyo Institute of Technology),  

[Date]2019-05-10
[Paper #]RECONF2019-18
A case study of system development based on software hardware co-design using an FPGA/CPU mixed SoC

Kenta Sato(TUT),  Yukinori Sato(TUT),  

[Date]2019-05-10
[Paper #]RECONF2019-13
Tsunami Simulation on FPGA by Exploiting Temporal Parallelism using OpenCL

Fumiya Kono(Kobe Univ.),  Naohito Nakasato(UoA),  

[Date]2019-05-10
[Paper #]RECONF2019-12
2次元拡散方程式のヤコビ法陰解法ソルバの高位合成によるストリーム実装

Yohei Sakamoto(Univ. Ryukyus),  Yasunori Osana(Univ. Ryukyus),  

[Date]2019-05-10
[Paper #]RECONF2019-11