Information and Systems-Image Engineering(Date:2017/09/25)

Presentation
Proplsal of reconfigurable system LSI with BiCS technology

Shigeyoshi Watanabe(Shonan Inst. of Tech.),  Tomohiro Yokota(DNP Data Techno),  Shouto Tamai(Oi Electric),  Takumi Sato(Japan Business Systems),  

[Date]2017-09-25
[Paper #]RECONF2017-28
A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization

Tomoya Fujii(Tokyo Inst. of Tech.),  Shimpei Sato(Tokyo Inst. of Tech.),  Hiroki Nakahara(Tokyo Inst. of Tech.),  

[Date]2017-09-25
[Paper #]RECONF2017-26
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme

Toru Homemoto(NTT),  Hisaharu Ishii(NTT),  Toshiya Matsuda(NTT),  Masaru Katayama(NTT),  Kazuyuki Matsumura(NTT),  

[Date]2017-09-25
[Paper #]RECONF2017-25
Hardware acceleration for holographic memories on optically reconfigurable gate arrays

Takumi Fujimori(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2017-09-25
[Paper #]RECONF2017-27
Pattern-matching-based game strategies and the strategy difference in pattern sizes

Masataka Nakano(Univ. of Tsukuba),  Yoshiki Yamaguchi(Univ. of Tsukuba),  

[Date]2017-09-25
[Paper #]RECONF2017-22
A thorough investigation of FPGA performance for PCIe Gen3 communication

Hiroki Nakamura(Univ. of Tsukuba),  Hirotaka Takayama(Univ. of Tsukuba),  Yoshiki Yamaguchi(Univ. of Tsukuba),  Taisuke Boku(Univ. of Tsukuba),  

[Date]2017-09-25
[Paper #]RECONF2017-23
Performance analysis of Mono-Instruction Set Computer using VTR

Hiroki Shinba(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2017-09-25
[Paper #]RECONF2017-29
ストリーム計算による拡散方程式の実装と性能評価

Yohei Sakamoto(Univ. of the Ryukyus),  Yasunori Osana(Univ. of the Ryukyus),  

[Date]2017-09-25
[Paper #]RECONF2017-24
[Invited Talk] Scalable and convertible FPGA DNN accelerator

Shinichi Suto(LeapMind),  Takato Yamada(LeapMind),  

[Date]2017-09-25
[Paper #]RECONF2017-30
カメラキャリブレーションのFPGA実装における高位合成記述の最適化に関する検討

Kazuya Uetsuhara(Nagasaki Univ.),  Hiroki Nagayama(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kiyoshi Oguri(Nagasaki Univ.),  

[Date]2017-09-26
[Paper #]RECONF2017-34
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler

Ryouzaburo Suzuki(Sinby),  Hiroaki Kataoka(Sinby),  

[Date]2017-09-26
[Paper #]RECONF2017-36
High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine

Shogo Nakamura(Univ. of Tsukuba),  Hiroki Ebara(Univ. of Tsukuba),  Kenji Kanazawa(Univ. of Tsukuba),  Noriyuki Aibe(Keio Univ.),  Moritoshi Yasunaga(Univ. of Tsukuba),  

[Date]2017-09-26
[Paper #]RECONF2017-32
GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA

Hiroki Nakahara(Tokyo Inst. of Tech.),  Haruyoshi Yonekawa(Tokyo Inst. of Tech.),  Tomoya Fujii(Tokyo Inst. of Tech.),  Masayuki Shimoda(Tokyo Inst. of Tech.),  Shimpei Sato(Tokyo Inst. of Tech.),  

[Date]2017-09-26
[Paper #]RECONF2017-31
A case study of High-level Synthesis Using Higher-order Function on Functional Language

Takuya Teraoka(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2017-09-26
[Paper #]RECONF2017-35
[Invited Talk] Increasing Productivity Using Xilinx Development Tools

Louie Valena(Xilinx),  

[Date]2017-09-26
[Paper #]RECONF2017-33