Information and Systems-Image Engineering(Date:2017/01/23)

Presentation
A Hardware Acceleration of Template Matching using FPGA and MPU

Yuji Matumoto(The University of Aizu),  Youichi Tomioka(The University of Aizu),  Junji Kitamichi(The University of Aizu),  

[Date]2017-01-23
[Paper #]VLD2016-70,CPSY2016-106,RECONF2016-51
Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes

Kousuke Tada(UEC),  Naoto Kawahara(UEC),  Masato Yoshimi(UEC),  Celimuge, Wu.(UEC),  Tsutomu Yoshinaga(UEC),  

[Date]2017-01-23
[Paper #]VLD2016-76,CPSY2016-112,RECONF2016-57
Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor

Akihiko Tsukahara(Tokyo Denki Univ.),  Akinori Kanasugi(Tokyo Denki Univ.),  

[Date]2017-01-23
[Paper #]VLD2016-71,CPSY2016-107,RECONF2016-52
A Case for FPGA Based 10GbE Switch Aggregating Computation Results of GPUs

Kazuma Takemoto(Keio Univ.),  Ami Hayashi(Keio Univ.),  Shin Morishima(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2017-01-23
[Paper #]VLD2016-77,CPSY2016-113,RECONF2016-58
GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application

Hiroshi Daisaka(Hitotsubashi Univ.),  Naohito Nakasato(Univ. of Aizu),  Tadashi Ishikawa(KEK),  Fukuko Yuasa(KEK),  Keigo Nitadori(RIKEN/AICS),  

[Date]2017-01-23
[Paper #]VLD2016-72,CPSY2016-108,RECONF2016-53
DCNNに最適なCGRAの探索と予備評価

Takahiro Ichikura(NAIST/KONICA MINOLTA, INC),  Ryusuke Yamano(NAIST),  Hisakazu Fukuoka(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2017-01-23
[Paper #]VLD2016-78,CPSY2016-114,RECONF2016-59
高速カメラを用いた可視光通信のための光源追跡モジュールの並列化の検討

Yu Nakahara(Ritumeikan Univ.),  Tomonori Izumi(Ritumeikan Univ.),  Lin Meng(Ritumeikan Univ.),  Yoshifumi Shiraki(NTT),  Yutaka Kamamoto(NTT),  Takehiro Moriya(NTT),  

[Date]2017-01-23
[Paper #]VLD2016-73,CPSY2016-109,RECONF2016-54
マルチFPGA上でのCNNの実装

Kazusa Musha(Keio Univ.),  Tomohiro Kudoh(Tokyo Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2017-01-23
[Paper #]VLD2016-90,CPSY2016-126,RECONF2016-71
CPU-FPGA混在クラスタにおけるリモート部分再構成の初期性能評価

Yasunori Osana(Univ. of the Ryukyus),  Yohei Sakamoto(Univ. of the Ryukyus),  Kousaku Matsuda(Univ. of the Ryukyus),  Shinya Okubo(Univ. of the Ryukyus),  

[Date]2017-01-23
[Paper #]VLD2016-74,CPSY2016-110,RECONF2016-55
Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection

Futoshi Murase(Kumamoto Univ),  Daichi Takagi(Kumamoto Univ),  Motoki Amagasaki(Kumamoto Univ),  Morihiro Kuga(Kumamoto Univ),  Masahiro Iida(Kumamoto Univ),  Toshinori Sueyoshi(Kumamoto Univ),  

[Date]2017-01-23
[Paper #]VLD2016-75,CPSY2016-111,RECONF2016-56
A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption

Kazumasa Ishikawa(Gunma Univ.),  Yuuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-92,CPSY2016-128,RECONF2016-73
FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data

Yuto Arai(Hiroshima City Univ.),  Shin'ichi Wakabayashi(Hiroshima City Univ.),  Shinobu Nagayama(Hiroshima City Univ.),  Masato Inagi(Hiroshima City Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-91,CPSY2016-127,RECONF2016-72
Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs

Thiem Van Chu(Tokyo Tech),  Kenji Kise(Tokyo Tech),  

[Date]2017-01-24
[Paper #]VLD2016-93,CPSY2016-129,RECONF2016-74
Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops

Yuki Kikuchi(Utsunomiya Univ.),  Kanemitsu Ootsu(Utsunomiya Univ.),  Takanobu Baba(Utsunomiya Univ.),  Takashi Yokota(Utsunomiya Univ.),  Takeshi Ohkawa(Utsunomiya Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-85,CPSY2016-121,RECONF2016-66
Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement

Haruyoshi Yonekawa(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  Masato Motomura(Hokkaido Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-88,CPSY2016-124,RECONF2016-69
Expression of Positional registers for Tamper resistance

Kiyohiro Sato(TUT),  Naoki Fujieda(TUT),  Shuichi Ichikawa(TUT),  

[Date]2017-01-24
[Paper #]VLD2016-86,CPSY2016-122,RECONF2016-67
A Case for Remote GPU Assignment for VR Applications

Shin Morishima(Keio Univ.),  Masahiro Okazaki(Keio Univ.),  Hiroki Matsutani(Keio Univ.PRESTO/NII),  

[Date]2017-01-24
[Paper #]VLD2016-82,CPSY2016-118,RECONF2016-63
Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption

Hiroaki Kaneko(Tokyo Denki Univ.),  Akinori Kanasugi(Tokyo Denki Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-87,CPSY2016-123,RECONF2016-68
［ショートペーパー］ニューラルネットワークのROS準拠FPGAコンポーネント化の初期検討

Takuya Matsumoto(Utsunomiya Univ.),  Kazushi Yamashina(Utsunomiya Univ.),  Takeshi Ohkawa(Utsunomiya Univ.),  Kanemitsu Ootsu(Utsunomiya Univ.),  Takashi Yokota(Utsunomiya Univ.),  

[Date]2017-01-24
[Paper #]VLD2016-89,CPSY2016-125,RECONF2016-70
A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization

Tomoya Fujii(Tokyo Tech),  Simpei Sato(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  Masato Motomura(Hokkaido univ.),  

[Date]2017-01-24
[Paper #]VLD2016-79,CPSY2016-115,RECONF2016-60
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