Information and Systems-Image Engineering(Date:2016/05/11)

Presentation
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures

Kotaro Terada(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2016-05-11
[Paper #]VLD2016-4
Self-Aligned Double Patterning-Aware Two-color Grid Routing

Hatsuhiko Miura(TUAT),  Mitsuru Hasegawa(TUAT),  Taku Hirukawa(TUAT),  Kunihiro Fujiyoshi(TUAT),  

[Date]2016-05-11
[Paper #]VLD2016-2
Multi bit soft error tolerant FPGA architecture

Yuji Nakamura(Kumamoto Univ.),  Takuya Teraoka(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Date]2016-05-11
[Paper #]VLD2016-3
A Note on Scheduling Problem Considering the Radiation Resistance of Registers

Keisuke Inoue(KTC),  Mineo Kaneko(JAIST),  

[Date]2016-05-11
[Paper #]
[Invited Talk] Challenges of DA Technologies for the Future

Michiaki Muraoka(Kochi Univ.),  

[Date]2016-05-11
[Paper #]VLD2016-6
MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA

Xushen Han(Waseda Univ.),  Dajiang Zhou(Waseda Univ.),  Shinji Kimura(Waseda Univ.),  

[Date]2016-05-11
[Paper #]VLD2016-5
An Application of Subgradient Method to Delay Analysis

Hiroshi Miyashita(The Univ. of Kitakyushu),  Koutaro Kawaraguchi(The Univ. of Kitakyushu),  

[Date]2016-05-11
[Paper #]VLD2016-1