Information and Systems-Image Engineering(Date:2016/02/17)

Presentation
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns

Naoya Ohsaki(NU),  Toshinori Hosokawa(NU),  Hiroshi Yamazaki(NU),  Masayoshi Yoshimura(KSU),  

[Date]2016-02-17
[Paper #]DC2015-93
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis

Hideyuki Takano(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Hiroshi Yamazaki(Nihon Univ.),  Koji Yamazaki(Meiji Univ.),  

[Date]2016-02-17
[Paper #]DC2015-91
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value

Kazui Fujitnai(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  

[Date]2016-02-17
[Paper #]DC2015-88
Study on the Effect of Power Supply Noise on Flip-Flop Circuits

Takuya Yamamoto(Tokyo Metropolitan Univ.),  Yukiya Miura(Tokyo Metropolitan Univ.),  

[Date]2016-02-17
[Paper #]DC2015-96
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

Fuqiang Li(Kyutech),  Xiaoqing Wen(Kyutech),  Stefan Holst(Kyutech),  Kohei Miyase(Kyutech),  Seiji Kajihara(Kyutech),  

[Date]2016-02-17
[Paper #]DC2015-87
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic

Keisuke Sonehara(Nihon Univ.),  Masayuki Arai(Nihon Univ.),  

[Date]2016-02-17
[Paper #]DC2015-86
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences

Kensuke Takamori(Hiroshima City Univ.),  Hideyuki Ichihara(Hiroshima City Univ.),  Tsuyoshi Iwagaki(Hiroshima City Univ.),  Tomoo Inoue(Hiroshima City Univ.),  

[Date]2016-02-17
[Paper #]DC2015-89
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding

Sayaka Satonaka(NAIST),  Tomokazu Yoneda(NAIST),  Yuta Yamato(NAIST),  Michiko Inoue(NAIST),  

[Date]2016-02-17
[Paper #]DC2015-92
Delay fault injection framework based on logic simulation with zero delay model

Shinji Kawasaki(NAIST),  Tomokazu Yoneda(NAIST),  Yuta Yamato(NAIST),  Michiko Inoue(NAIST),  

[Date]2016-02-17
[Paper #]DC2015-90
The Hybrid Communication Protocol for CANs

Koji Konomi(Tokyo Metropolitan Univ.),  Muneyuki Nakamura(Tokyo Metropolitan Univ.),  Kazuya Sakai(Tokyo Metropolitan Univ.),  Satoshi Fukumoto(Tokyo Metropolitan Univ.),  

[Date]2016-02-17
[Paper #]DC2015-95
Analog Circuit Design for a Precision Resistance Measurement of TSVs

Senling Wang(Ehime Univ.),  Keisuke Kagawa(Ehime Univ.),  Shuichi Kameyama(Fujitsu),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  

[Date]2016-02-17
[Paper #]DC2015-94