IEICE Technical Committee

[Date]2016-01-19
[Paper #]VLD2015-77,CPSY2015-109,RECONF2015-59

Cost Estimation Method based on CPU Architecture for Relational Database Query Optimization

Tsuyoshi Tanaka(Tokyo Metropolitan Univ./Hitachi), Hiroshi Ishikawa(Tokyo Metropolitan Univ.),

[Date]2016-01-19
[Paper #]VLD2015-84,CPSY2015-116,RECONF2015-66

Performance Improvement on In-Kernel NOSQL Cache for Range Queries

Korechika Tamura(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2016-01-19
[Paper #]VLD2015-85,CPSY2015-117,RECONF2015-67

Performance Evaluations on Reduction and Transformation of Spark Using GPU

Yasuhiro Ohno(Keio Univ.), Shin Morishima(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2016-01-19
[Paper #]VLD2015-81,CPSY2015-113,RECONF2015-63

GPGPU Parallelization of a cerebral cortex model BESOM

Hidemoto Nakada(AIST), Tatsuhiko Inoue(AIST), Yuji Ichisugi(AIST),

[Date]2016-01-19
[Paper #]VLD2015-82,CPSY2015-114,RECONF2015-64

GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation

Shotaro Asano(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.),

[Date]2016-01-19
[Paper #]VLD2015-83,CPSY2015-115,RECONF2015-65

FPGA routing structure based on H-Tree topology

Yuki ishii(Kumamoto Univ.), Masato Ikebe(Kumamoto Univ.), Qian Zhao(Kumamoto Univ.), Motoki Amagasaki(Kumamoto Univ.), Masahiro Iida(Kumamoto Univ.), Morihiro Kuga(Kumamoto Univ.), Toshinori Sueyoshi(Kumamoto Univ.),

[Date]2016-01-19
[Paper #]VLD2015-78,CPSY2015-110,RECONF2015-60

FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams

Yoshimitsu Ogawa(UEC), Yasin Oge(UEC), Masato Yoshimi(UEC), Celimuge Wu(UEC), Tsutomu Yoshinaga(UEC),

[Date]2016-01-19
[Paper #]VLD2015-86,CPSY2015-118,RECONF2015-68

Pipelining in Coarse Grained Reconfigurable Accelerator CMA

Naoki Ando(Keio Univ.), Koichiro Masuyama(Keio Univ.), Yu Fujita(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2016-01-19
[Paper #]VLD2015-79,CPSY2015-111,RECONF2015-61

A Low-Latency Batch Processing for Stream Data Using FPGA NIC

Kohei Nakamura(Keio Univ.), Ami Hayashi(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2016-01-19
[Paper #]VLD2015-80,CPSY2015-112,RECONF2015-62

Topological Analysis of Low-Powered 3D-TESH Network

Faiz Al Faisal(JAIST), Hafizur Rahman(IIUM), Yasushi Inoguchi(JAIST),

[Date]2016-01-20
[Paper #]VLD2015-94,CPSY2015-126,RECONF2015-76

A Chip Evaluation of the Heat Generation in 3D stacked LSI

Tatsuya Wada(Shibaura IT), Kimiyosi Usami(Shibaura IT),

[Date]2016-01-20
[Paper #]VLD2015-87,CPSY2015-119,RECONF2015-69

Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX

Shohei Io(Shibaura IT), Hanano Suzuki(Shibaura IT), Shohei Nakamura(Shibaura IT), Kimiyoshi Usami(Shibaura IT),

[Date]2016-01-20
[Paper #]VLD2015-88,CPSY2015-120,RECONF2015-70

Control Signal Extraction for Backward Sequential Clock Gating

Tomoya Goto(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Shinji Kimura(Waseda Univ.),

[Date]2016-01-20
[Paper #]VLD2015-89,CPSY2015-121,RECONF2015-71

Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis

Rie Soejima(Nagasaki Univ.), Koji Okina(Nagasaki Univ.), Yuichiro Shibata(Nagasaki Univ.), Kiyoshi Oguri(Nagasaki Univ.),

[Date]2016-01-20
[Paper #]VLD2015-91,CPSY2015-123,RECONF2015-73

An Efficient NoC with Decentralized Routers

Ryota Yasudo(Keio Univ.), Hiroki Matsutani(Keio Univ.), Michihiro Koibuchi(NII), Hideharu Amano(Keio Univ.), Tadao Nakamura(Keio Univ.),

[Date]2016-01-20
[Paper #]VLD2015-95,CPSY2015-127,RECONF2015-77

FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler

Kohei Nagasu(Tohoku Univ.), Kentaro Sano(Tohoku Univ.), Fumiya Kono(The Univ. of Aizu), Naohito Nakasato(The Univ. of Aizu),

[Date]2016-01-20
[Paper #]VLD2015-92,CPSY2015-124,RECONF2015-74

A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation

Yusuke Haga(Hiroshima City Univ.), Shinobu Nagayama(Hiroshima City Univ.), Shin'ichi Wakabayashi(Hiroshima City Univ.), Masato Inagi(Hiroshima City Univ.),

[Date]2016-01-20
[Paper #]VLD2015-93,CPSY2015-125,RECONF2015-75

A performance evaluation of PEACH3

Takahiro Kaneda(Keio Univ), Chiharu Tsuruta(Keio Univ), Toshihiro Hanawa(UTokyo), Hideharu Amano(Keio Univ),

[Date]2016-01-20
[Paper #]VLD2015-96,CPSY2015-128,RECONF2015-78

Latency Reduction on Inter-Component Communication across Racks using FSO

Hiroaki Hara(Keio Univ.), Tomoya Ozaki(Keio Univ.), Michihiro Koibuchi(NII), Hideharu Amano(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2016-01-20
[Paper #]VLD2015-97,CPSY2015-129,RECONF2015-79