Information and Systems-Image Engineering(Date:2015/05/14)

Presentation
Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits

Tomoya Goto(Waseda Univ.),  Kohei Higuchi(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Shinji Kimura(Waseda Univ.),  

[Date]2015-05-14
[Paper #]VLD2015-4
Use of the subgradient method to minimize half perimeter wirelength with consideration of cell overlap in analytical placement

Hiroyuki Iwasaki(The Univ. of Kitakyushu),  Hiroshi Miyashita(The Univ. of Kitakyushu),  

[Date]2015-05-14
[Paper #]VLD2015-2
AES Encryption Circuit against Clock Glitch based Fault Analysis

Daisuke Hirano(Waseda Univ),  Youhua Shi(Waseda Univ),  Nozomu Togawa(Waseda Univ),  Masao Yanagisawa(Waseda Univ),  

[Date]2015-05-14
[Paper #]VLD2015-7
Power Analysis Method for a Lightweight Block Cipher Simon

Yusuke Nozaki(Meijo Univ.),  Masaya Yoshikawa(Meijo Univ.),  

[Date]2015-05-14
[Paper #]VLD2015-6
NP-completeness of Routing Problem with Bend Constraint

Toshiyuki Hongo(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  

[Date]2015-05-14
[Paper #]VLD2015-3
A minimum test pattern set generation for large circuits

Yusuke Matsunaga(Kyushu Univ.),  

[Date]2015-05-14
[Paper #]VLD2015-1
[Invited Talk] Trends and Future Challenges of Nano-electronics R&D in Japan

Seiichiro Kawamura(JST),  

[Date]2015-05-14
[Paper #]VLD2015-5