Information and Systems-Image Engineering(Date:2005/10/14)

Presentation
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[Date]2005/10/14
[Paper #]
目次

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[Date]2005/10/14
[Paper #]
A Phase Noise Minimization of CMOS LC-VCOs over Wide Tuning Range and Large PVT Variations

Daisuke MIYASHITA,  Hiroki ISHIKURO,  Shouhei KOUSAI,  Hiroyuki KOBAYASHI,  Hideaki MAJIMA,  Kenichi AGAWA,  Mototsugu HAMADA,  

[Date]2005/10/14
[Paper #]SIP2005-115,ICD2005-134,IE2005-79
Substrate-Noise and Random-Fluctuations Reduction with Self-Adjusted Forward Body Bias

Yoshihide Komatsu,  Koichiro Ishibashi,  Toshiro Tsukada,  Masaharu Yamamoto,  Kenji Shimazaki,  Mitsuya Fukazawa,  Makoto Nagata,  

[Date]2005/10/14
[Paper #]SIP2005-116,ICD2005-135,IE2005-80
Thermal Analysis on Microprocessors

Naoyuki HASEGAWA,  MUTSUO Ito,  Ryusuke EGAWA,  Kenichi SUZUKI,  Tadao NAKAMURA,  

[Date]2005/10/14
[Paper #]SIP2005-117,ICD2005-136,IE2005-81
Development of an embedded processor core SH-X2

Takashi OKADA,  Tomoichi HAYASHI,  Takehiro SHIMIZU,  Fumio ARAKAWA,  Tetsuya YAMADA,  Osamu NISHII,  Toshihiro HATTORI,  

[Date]2005/10/14
[Paper #]SIP2005-118,ICD2005-137,IE2005-82
Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors

Atsushi TANAKA,  Atsuhiro SUGA,  Fumihiko HAYAKAWA,  Shinichiro TAGO,  Satoshi IMAI,  

[Date]2005/10/14
[Paper #]SIP2005-119,ICD2005-138,IE2005-83
Compaction of Arithmetic Unit with Bit-Level-Parallelism

Jubei TADA,  Ryusuke EGAWA,  Gensuke GOTO,  Tadao NAKAMURA,  

[Date]2005/10/14
[Paper #]SIP2005-120,ICD2005-139,IE2005-84
Configurable Processor MeP and its SoC Design Examples

Takashi Miyamori,  

[Date]2005/10/14
[Paper #]SIP2005-121,ICD2005-140,IE2005-85
Technological Trend of Embedded Processors : Achieving Both High-performance and Low-power

Kunio UCHIYAMA,  

[Date]2005/10/14
[Paper #]SIP2005-122,ICD2005-141,IE2005-86
A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems

Makoto SUGIHARA,  Tohru ISHIHARA,  Koji HASHIMOTO,  Masanori MUROYAMA,  

[Date]2005/10/14
[Paper #]SIP2005-123,ICD2005-142,IE2005-87
A study for hardware optimization using a high level synthesis from C

Satoru Inoue,  Tsuyoshi Kondo,  Tomonori Izumi,  Masahiro Fukui,  

[Date]2005/10/14
[Paper #]SIP2005-124,ICD2005-143,IE2005-88
A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches

Tohru ISHIHARA,  Farzan FALLAH,  

[Date]2005/10/14
[Paper #]SIP2005-125,ICD2005-144,IE2005-89
A study for power and speed tradeoff estimation from behavioral hardware model

Noriyuki Inoue,  Katsuhiro Oshikawa,  Tomonori Izumi,  Masahiro Fukui,  

[Date]2005/10/14
[Paper #]SIP2005-126,ICD2005-145,IE2005-90
A Monitor Generation Method for Formal Monitor-based Verification Considering Input Constraints

Yosuke KAKIUCHI,  Akira KITAJIMA,  Kiyoharu HAMAGUCHI,  Toshinobu KASHIWABARA,  

[Date]2005/10/14
[Paper #]SIP2005-127,ICD2005-146,IE2005-91
A cell library development methodology for character projection

Makoto SUGIHARA,  Taiga TAKATA,  Kenta NAKAMURA,  Ryoichi INANAMI,  Hiroaki HAYASHI,  Katsumi KISHIMOTO,  Tetsuya HASEBE,  Yukihiro KAWANO,  Yusuke MATSUNAGA,  Kazuaki MURAKAMI,  Katsuya OKUMURA,  

[Date]2005/10/14
[Paper #]SIP2005-128,ICD2005-147,IE2005-92
A Study for Power Grid Optimization

Taiki Harada,  Kenji Kusano,  Takayuki Shimada,  Hironobu Ishijima,  Masahiro Fukui,  

[Date]2005/10/14
[Paper #]SIP2005-129,ICD2005-148,IE2005-93
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