Information and Systems-Image Engineering(Date:1999/10/29)

Presentation
表紙

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[Date]1999/10/29
[Paper #]
目次

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[Date]1999/10/29
[Paper #]
On blind source separation by genetic algorithms

Shuichi Ohno,  Hiromitsu Karei,  Sadayoshi Hirai,  Yujiro Inouye,  

[Date]1999/10/29
[Paper #]IE99-60
Closed-Form Design of Variable Fractional Delay Filters

Wu-Sheng Lu,  Tian-Bo Deng,  

[Date]1999/10/29
[Paper #]IE99-61
Steady State Analysis of an Adaptive Notch Filter Using Normalized Gradient Algorithm

Yuichi Sawada,  Shotaro Nisimura,  

[Date]1999/10/29
[Paper #]IE99-62
A Study on Adaptive Notch Filter Utilizing an Allpass Filter

Shin'ichi Arita,  James Okello,  Yoshio Itoh,  Yutaka Fukui,  Masaki Kobayashi,  

[Date]1999/10/29
[Paper #]IE99-63
Influence of screen size and viewing distance on the psychological parameters of wide visual field images

Nagato NARITA,  Masaru KANAZAWA,  

[Date]1999/10/29
[Paper #]IE99-64
Lossless 8-point fast discrete cosine transform using lossless hadamard transform

Shinji FUKUMA,  Koichi OHYAMA,  Masahiro IWAHASHI,  Noriyoshi KAMBAYASHI,  

[Date]1999/10/29
[Paper #]IE99-65
Right-Brain Computing Integrated Circuits for Intelligent Information Processing

Tadashi SHIBATA,  Masakazu Yagi,  Masayoshi Adachi,  

[Date]1999/10/29
[Paper #]IE99-66
A study on decision method of architecture for image processing processor (1) : Methodology of selecting instruction set from application program

Tomoyuki Sudo,  Arata Miyauchi,  Tomoo Ishikawa,  

[Date]1999/10/29
[Paper #]IE99-67
Fast Breaking-off-search (BOS) Motion Estimation Algorithm for MPEG-2 and Low-Power CMOS Absolute Difference Accumulator LSI

Homoon Kim,  Y. Sasajima,  A. Katabe,  J. Matsumoto,  T. Enomoto,  

[Date]1999/10/29
[Paper #]IE99-68
MPEG2MP@HL Decoder LSI for Digital TVs

Yasuhiro Watanabe,  Hidenaga Takahashi,  Koji Yoshitomi,  Yukio Otobe,  Kiyoshi Kohiyama,  

[Date]1999/10/29
[Paper #]IE99-69
A single chip digital TV LSI with a flexible 2D graphic processor utilized optimizing memory architecture

Eiichiro Tomonaga,  Masahiro Yamada,  

[Date]1999/10/29
[Paper #]IE99-70
Development of an MPEG-2 422@HL encoder chip set for higher quality coding

Eiji Ohara,  Toshiaki Shimada,  Akira Kotani,  Yoshinori Matsuura,  Tadashi Kasezawa,  Ken-ichi Asano,  Masahiko Yoshimoto,  

[Date]1999/10/29
[Paper #]IE99-71
Issue control logic implementation and delay improvement for multimedia processor SH4-CPU

Takanobu Tsunoda,  Osamu Nishii,  Fumio Arakawa,  Sadaki Nakano,  Tetsuya Yamada,  Tomoichi Hayashi,  Kunio Uchiyama,  Toshihiro Hattori,  Norio Nakagawa,  Susumu Narita,  Ryuichi Satomura,  Mitsuho Seki,  

[Date]1999/10/29
[Paper #]IE99-72
A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on PWM Method

H. Nakamoto,  M. Nagata,  T. Morie,  A. Iwata,  

[Date]1999/10/29
[Paper #]IE99-73
[OTHERS]

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[Date]1999/10/29
[Paper #]