Information and Systems-Dependable Computing(Date:2018/02/20)

A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation

Yuki Takeuchi(Nihon Univ.),  Shun Takeda(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Hiroshi Yamazaki(Nihon Univ.),  Masayoshi Yoshimura(Kyoto Sangyo Univ.),  

[Paper #]DC2017-78
Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure

Kouhei Satou(Tokyo Metropolitan Univ.),  Yukiya Miura(Tokyo Metropolitan Univ.),  

[Paper #]DC2017-86
Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures

Miyuki Inoue(Tokyo Metropolitan Univ.),  Yukiya Miura(Tokyo Metropolitan Univ.),  

[Paper #]DC2017-88
On generating locating arrays using simulated annealing

Tatsuya Konishi(Osaka Univ.),  Hideharu Kojima(Osaka Univ.),  Hiroyuki Nakagawa(Osaka Univ.),  Tatsuhiro Tsuchiya(Osaka Univ.),  

[Paper #]DC2017-82
A test generation method based on k-cycle testing for finite state machines

Yuya Kinoshita(Nihon Univ.),  Toshinori Hosokawa(Nihon Univ.),  Hideo Fujiwara(Osaka Gakuin Univ.),  

[Paper #]DC2017-81
A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation

Fakir Sharif Hossain(NAIST),  Tomokazu Yoneda(NAIST),  Michihiro Shintani(NAIST),  Michiko Inoue(NAIST),  Alex Orailoglu(Univ. of California, San Diego),  

[Paper #]DC2017-84
A Note on Stateless Avoidance Routing in Ad Hoc Networks

Tomonori Maeda(Tokyo Metropolitan Univ.),  Kazuya Sakai(Tokyo Metropolitan Univ.),  Satoshi Fukumoto(Tokyo Metropolitan Univ.),  

[Paper #]DC2017-83
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD)

Senling Wang(Ehime Univ.),  Tatsuya Ogawa(Ehime Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  Masayuki Sato(TRL),  Mitsunori Katsu(TRL),  Shoichi Sekiguchi(TAIYOYUDEN),  

[Paper #]DC2017-87
Note on Weighted Fault Coverage for Two-Pattern Tests

Masayuki Arai(Nihon Univ.),  Kazuhiko Iwasaki(Tokyo Metro. Univ.),  

[Paper #]DC2017-77
A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor

Kenji Inoue(Kyutech),  Yousuke Miyake(Kyutech),  Seiji Kajihara(Kyutech),  

[Paper #]DC2017-85
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC

Satoshi Hirai(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  

[Paper #]DC2017-79
Locating Hot Spots with Justification Techniques in a Layout Design

Yudai Kawano(Kyutech),  Kohei Miyase(Kyutech),  Seiji Kajihara(Kyutech),  Xiaoqing Wen(Kyutech),  

[Paper #]DC2017-80