Information and Systems-Dependable Computing(Date:2014/02/03)

Presentation
表紙

,  

[Date]2014/2/3
[Paper #]
目次

,  

[Date]2014/2/3
[Paper #]
Module Coupling Overhead Aware Scan Chain Construction

Meguru KOMATSU,  Hiroshi IWATA,  Ken'ich YAMAGUCHI,  

[Date]2014/2/3
[Paper #]DC2013-79
On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan

Hiroki SAKURAI,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2014/2/3
[Paper #]DC2013-80
A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit

Sanae MIZUTANI,  Hiroshi IWATA,  Ken'ichi YAMAGUCHI,  

[Date]2014/2/3
[Paper #]DC2013-81
Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path

Ryo OGAWA,  Hiroshi IWATA,  Ken'ichi YAMAGUCHI,  

[Date]2014/2/3
[Paper #]DC2013-82
A Low Power Dissipation Oriented Don't Care Filling Method Using SAT

Yoshiyasu TAKAHASHI,  Hiroshi YAMAZAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2014/2/3
[Paper #]DC2013-83
Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open

Yuta Nakayama,  Masayuki Arai,  Hongbo Shi,  Kazuhiko Iwasaki,  

[Date]2014/2/3
[Paper #]DC2013-84
Device-parameter Estimation Based on F_ Testing

Michihiro SHINTANI,  Takashi SATO,  

[Date]2014/2/3
[Paper #]DC2013-85
An Efficient Test Pattern Generator based on Mersenne Twister algorithm

Sayaka SATONAKA,  Hiroshi IWATA,  Ken'ichi YAMAGUCHI,  

[Date]2014/2/3
[Paper #]DC2013-86
A reduction method of shift data volume on BAST

Marika TANAKA,  Hiroshi YAMAZAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  Masayuki ARAI,  

[Date]2014/2/3
[Paper #]DC2013-87
Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code

Ryota MORI,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2014/2/3
[Paper #]DC2013-88
A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation

Hiroshi YAMAZAKI,  Yuto KAWATSURE,  Jun NISHIMAKI,  Atsushi HIRAI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  Koji YAMAZAKI,  

[Date]2014/2/3
[Paper #]DC2013-89
An Implementation of Fault Tolerant Systems with Mutual Reconfiguration Based on Dual-FPGA Architecture

Takuma MORI,  Shouichi OHMOTO,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2014/2/3
[Paper #]DC2013-90
Detection of Wormhole Attack in Wireless Sensor Network with XMesh Protocol

Takashi MINOHARA,  Aoi YOSHII,  

[Date]2014/2/3
[Paper #]DC2013-91
複写される方へ

,  

[Date]2014/2/3
[Paper #]
Notice for Photocopying

,  

[Date]2014/2/3
[Paper #]
奥付

,  

[Date]2014/2/3
[Paper #]
裏表紙

,  

[Date]2014/2/3
[Paper #]