Information and Systems-Dependable Computing(Date:2013/11/20)

Presentation
表紙

,  

[Date]2013/11/20
[Paper #]
目次

,  

[Date]2013/11/20
[Paper #]
A VLSI algorithm for computing correctly rounded hypotenuse

Hiroyuki YATAKA,  Naofumi TAKAGI,  

[Date]2013/11/20
[Paper #]VLD2013-61,DC2013-27
Fast distance calculation method for rooted tree with CUDA

Hiroki SAKAMOTO,  Yasuhiro TAKASHIMA,  

[Date]2013/11/20
[Paper #]VLD2013-62,DC2013-28
Adjacent Common Centroid Placement for Analog IC Layout Design

Kenichiro MUROTATSU,  Kunihiro FUJIYOSHI,  

[Date]2013/11/20
[Paper #]VLD2013-63,DC2013-29
An Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips

Trung ANH DINH,  Shigeru YAMASHITA,  Tsung-Yi HO,  

[Date]2013/11/20
[Paper #]VLD2013-64,DC2013-30
Minimal fab : One by one manufacturing of devices

Shiro Hara,  Hitoshi Maekawa,  Shinichi Ikeda,  Shizuka Nakano,  Sommawan Khumpuang,  

[Date]2013/11/20
[Paper #]Vol.2013-SLDM-163 No.5
A Heuristic Design Method for Yield Improvement based on PPCs

Shunichi SANAE,  Yuko HARA-AZUMI,  Shigeru YAMASHITA,  Yasuhiko NAKASHIMA,  

[Date]2013/11/20
[Paper #]VLD2013-65,DC2013-31
Fault-Tolerant Design with Less Overhead than DMR

Atsushi MATSUO,  Shigeru YAMASHITA,  

[Date]2013/11/20
[Paper #]VLD2013-66,DC2013-32
Suspicious timing error prediction using check points

Hiroaki IGARASHI,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2013/11/20
[Paper #]VLD2013-67,DC2013-33
A Controller Design in High-Level Synthesis for Multi-Cycle Transient Fault Tolerance

Yutaro ISHIMORI,  Tatsuya NAKASO,  Tsuyoshi IWAGAKI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2013/11/20
[Paper #]VLD2013-68,DC2013-34
A Parallel Logic Simulation method based on Multi-core Processor

Wenzhu Dou,  Yuya Takeuchi,  Masahiko Toyonaga,  Michiaki Muraoka,  

[Date]2013/11/20
[Paper #]Vol.2013-SLDM-163 No.10
A Logic Simulation Method using FPGA

Natsuki Matsumoto,  Michiaki Muraoka,  

[Date]2013/11/20
[Paper #]Vol.2013-SLDM-163 No.11
A Hardware/Software Simulator for NoC using SystemC and QEMU

Yosuke Kurimoto,  Yusuke Fukutsuka,  Ittetsu Taniguchi,  Hiroyuki Tomiyama,  

[Date]2013/11/20
[Paper #]VLD2013-69,DC2013-35
FPGAを対象とした束データ方式による非同期式回路の設計支援ツールセット(設計支援,デザインガイア2013-VLSI設計の新しい大地-)

KEITARO TAKIZAWA,  HIROSHI SAITO,  

[Date]2013/11/20
[Paper #]Vol.2013-SLDM-163 No.13
Improved via programmable structured ASIC VPEX3S : Improvement of basic logic element to improve operation speed

Taku Otani,  Ryohei Hori,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2013/11/20
[Paper #]VLD2013-70,DC2013-36
New Via Programmable Architecture VPEX4 (1) : Development of new logic element for improvement of routability and power consumption

Ryohei Hori,  Taku Otani,  Tatsuro Hitomi,  Syota Ueguchi,  Masaya Yosikawa,  Takeshi Fujino,  

[Date]2013/11/20
[Paper #]VLD2013-71,DC2013-37
Evaluation of Via Programmable Device named VPEX using benchmark circuits

Shota Ueguchi,  Ryohei Hori,  Taku Otani,  Masaya Yoshikawa,  Takeshi Fujino,  

[Date]2013/11/20
[Paper #]VLD2013-72,DC2013-38
Circuit design for 3D-stacking using TSV interconnects

Kenichi Osada,  Futoshi Furuta,  Kenichi Takeda,  

[Date]2013/11/20
[Paper #]VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators

Yasuhiro Take,  Noriyuki Miura,  Hiroki Ishikuro,  Tadahiro Kuroda,  

[Date]2013/11/20
[Paper #]VLD2013-74,CPM2013-118,ICD2013-95,CPSY2013-59,DC2013-40,RECONF2013-42
123>> 1-20hit(57hit)