Information and Systems-Dependable Computing(Date:2011/11/21)

Presentation
表紙

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[Date]2011/11/21
[Paper #]
目次

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[Date]2011/11/21
[Paper #]
The RG-DTM PUF utilizing the Time to Digital Converter

Takahiko MURAYAMA,  Mitsuru SHIOZAKI,  Kota FURUHASHI,  Takeshi FUJINO,  

[Date]2011/11/21
[Paper #]VLD2011-52,DC2011-28
Scan-based Attack against Triple DES Cryptosystems Using Scan Signatures

Hirokazu KODERA,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2011/11/21
[Paper #]VLD2011-53,DC2011-29
On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents

Katsuya FUJIWARA,  Hideo FUJIWARA,  Hideo TAMAMOTO,  

[Date]2011/11/21
[Paper #]VLD2011-54,DC2011-30
Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA

Shouhei ISHII,  Kazutoshi KOBAYASHI,  

[Date]2011/11/21
[Paper #]VLD2011-55,DC2011-31
High accuracy of system LSI energy estimation

Xiang Wang,  Norifumi YOSHIMATSU,  Kazuaki MURAKAMI,  

[Date]2011/11/21
[Paper #]VLD2011-56,DC2011-32
An Interrupt Service Handler in Hardware for Ultra-Low Latency Response

Naotaka MARUYAMA,  Tohru ISHIHARA,  Hiroaki TAKADA,  Hiroto YASUURA,  

[Date]2011/11/21
[Paper #]VLD2011-57,DC2011-33
Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links

Atsushi MATSUMOTO,  Naoya ONIZAWA,  Takahiro HANYU,  

[Date]2011/11/21
[Paper #]VLD2011-58,DC2011-34
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops

Shogo OKADA,  Masaki MASUDA,  Jun YAO,  Hajime SHIMADA,  Kazutoshi KOBAYASHI,  

[Date]2011/11/21
[Paper #]VLD2011-59,DC2011-35
A Dynamically Configurable NoC Test Access Mechanism

Takieddine SBIAI,  Kazuteru NAMBA,  Hideo ITO,  

[Date]2011/11/21
[Paper #]VLD2011-60,DC2011-36
A Consideration on Wire-Sizing of Input Signals for System on Glass Liquid Crystal Display

Taichi SUIZU,  Shuji TSUKIYAMA,  

[Date]2011/11/21
[Paper #]VLD2011-61,DC2011-37
Analytical Placement for Convex Blocks

Tomoaki GOTANDA,  Masatomo KUWANO,  Yasuhiro TAKASHIMA,  

[Date]2011/11/21
[Paper #]VLD2011-62,DC2011-38
An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm

Takumi MORISHITA,  Hiroshi TSUTSUI,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2011/11/21
[Paper #]VLD2011-63,DC2011-39
A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling

Tetsuro MIYAKAWA,  Hiroshi TSUTSU,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2011/11/21
[Paper #]VLD2011-64,DC2011-40
CMOS Op-amp Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String DAC

Hiroyuki Morimoto,  Hiroaki Goto,  Hajime Fujiwara,  Kazuyuki Nakamura,  

[Date]2011/11/21
[Paper #]VLD2011-65,DC2011-41
A study on parameter estimation for modeling of random-telegraph noise

Hiromitsu AWANO,  Hirofumi SHIMIZU,  Hiroshi TSUTSUI,  Hiroyuki OCHI,  Takashi SATO,  

[Date]2011/11/21
[Paper #]VLD2011-66,DC2011-42
Synthesis of efficient data fetch mechanism from the high level communication description

Masato MINATO,  Yuki ANDO,  Seiya SHIBATA,  Tomoo KINOSHITA,  Shinya HONDA,  Hiroaki TAKADA,  

[Date]2011/11/21
[Paper #]VLD2011-67,DC2011-43
A Runtime Mechanism for Managing of the Scratch-pad Memory within Real-Time Operating Systems

Hideki TAKASE,  Hiroaki TAKADA,  

[Date]2011/11/21
[Paper #]VLD2011-68,DC2011-44
Automatic Loop Fusion for High Level Synthesis using Outer Loop Shifting

Yuta KATO,  Kenshu SETO,  Takuya MARUIZUMI,  

[Date]2011/11/21
[Paper #]VLD2011-69,DC2011-45
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