Information and Systems-Dependable Computing(Date:2011/06/17)

Presentation
表紙

,  

[Date]2011/6/17
[Paper #]
目次

,  

[Date]2011/6/17
[Paper #]
An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults

Satoshi FUKUMOTO,  Masayuki ARAI,  Shinya HARA,  Kazuhiko IWASAKI,  

[Date]2011/6/17
[Paper #]DC2011-8
Effective Multi-cycle Signatures in Testable Response Analyzers

Yuki FUKAZAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2011/6/17
[Paper #]DC2011-9
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI

Satoshi KASHIWAZAKI,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2011/6/17
[Paper #]DC2011-10
International Conference Report : VTS2011(29th IEEE VLSI Test Symposium)

Kazumi HATAYAMA,  

[Date]2011/6/17
[Paper #]DC2011-11
A don't care identification method with care bit distribution control : Application to capture power reduction

Hiroshi Yamazaki,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2011/6/17
[Paper #]DC2011-12
Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification

K. MIYASE,  Y. UCHINODAN,  K. ENOKIMOTO,  Y. YAMATO,  X. WEN,  S. KAJIHARA,  F. WU,  L. DILILLO,  A. BOSIO,  P. GIRARD,  A. VIRAZEL,  

[Date]2011/6/17
[Paper #]DC2011-13
複写される方へ

,  

[Date]2011/6/17
[Paper #]
奥付

,  

[Date]2011/6/17
[Paper #]
裏表紙

,  

[Date]2011/6/17
[Paper #]