Information and Systems-Dependable Computing(Date:2010/11/22)

Presentation
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[Date]2010/11/22
[Paper #]
目次

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[Date]2010/11/22
[Paper #]
An Approach to Translate from Mathematical to Electronic Descriptions of Image Processing Algorithm for ITS

Yukio FUJITA,  Masanori TSUZUKI,  Yoshiya SUGITA,  Masahiro FUKUI,  

[Date]2010/11/22
[Paper #]VLD2010-57,DC2010-24
Rapid SoC Prototyping Based on Virtual Multi-Processor Model

Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2010/11/22
[Paper #]VLD2010-58,DC2010-25
A Scalable Heuristic for Incremental High-Level Synthesis

Shohei ONO,  Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2010/11/22
[Paper #]VLD2010-59,DC2010-26
A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths

Hayato HENMI,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2010/11/22
[Paper #]VLD2010-60,DC2010-27
Evaluation of Multi-Cycle Test with Partial Observation in Scan-Based BIST Structure

Hisato YAmAGUCHI,  Makoto MATSUZONO,  Yasuo SATO,  Seiji KAJIHARA,  

[Date]2010/11/22
[Paper #]VLD2010-61,DC2010-28
A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation

Yang SHEN,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2010/11/22
[Paper #]VLD2010-62,DC2010-29
Experimental Evaluation of Built-in Test Pattern Generation with Image

Yuka IWAMOTO,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2010/11/22
[Paper #]VLD2010-63,DC2010-30
Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy

Masashi TAWADA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  Nozomu TOGAWA,  

[Date]2010/11/22
[Paper #]VLD2010-64,DC2010-31
Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors

Ittetsu TANIGUCHI,  Mitsuya UCHIDA,  Hiroyuki TOMIYAMA,  Masahiro FUKUI,  

[Date]2010/11/22
[Paper #]VLD2010-65,DC2010-32
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes

Satoshi TAKEYASU,  Masashi IMAI,  Hiroshi NAKAMURA,  

[Date]2010/11/22
[Paper #]VLD2010-66,DC2010-33
FPGA design and test methodology for communication frame processing

Ritsu KUSABA,  Kenji KAWAI,  Sadayuki YASUDA,  Satoshi SHIGEMATSU,  Mamoru NAKANISHI,  Masami URANO,  

[Date]2010/11/22
[Paper #]VLD2010-67,DC2010-34
Evaluation of FPGA Implementation Techniques for High-Performance So Prototypes

Hideo TANIDA,  Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Date]2010/11/22
[Paper #]VLD2010-68,DC2010-35
Paper Writing Guide for International Conferences : Implications in VLSI design methodology field

Masanori Hashimoto,  

[Date]2010/11/22
[Paper #]VLD2010-69,DC2010-36
Accurate Delay Analysis Method of Power-Gated Circuit

Seidai TAKEDA,  Kyundong KIM,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  

[Date]2010/11/22
[Paper #]VLD2010-70,DC2010-37
Photonic-electronic Convergence Technology Based on Silicon. : Integration of photonic and electric circuits utilizing Siliconphotonics

Seiichi ITABASHI,  Tai TSUCHIZAWA,  Koji YAMADA,  Toshifumi WATANABE,  Hiroyuki SHINOSHIMA,  Hideaki NISHI,  Rai TAKAHASHI,  Kazumi WADA,  Yasuhiko ISHIKAWA,  

[Date]2010/11/22
[Paper #]VLD2010-71,DC2010-38
SREEP : A Tool for Secure Scan Design Using Shift Register Equivalents

Katsuya FUJIWARA,  Hideo FUJIWARA,  Hideo TAMAMOTO,  

[Date]2010/11/22
[Paper #]VLD2010-72,DC2010-39
Fault-Injection using Virtualized Environment for Validating Automotive Systems

Yasuhiro ITO,  Yohei NAKATA,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  Yasuo SUGURE,  Shigeru OHO,  

[Date]2010/11/22
[Paper #]VLD2010-73,DC2010-40
Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme

Yohei NAKATA,  Yasuhiro ITO,  Yasuo SUGURE,  Shigeru OHO,  Hiroko KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2010/11/22
[Paper #]VLD2010-74,DC2010-41
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