Information and Systems-Dependable Computing(Date:2010/06/18)

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[Date]2010/6/18
[Paper #]
目次

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[Date]2010/6/18
[Paper #]
A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths

Hiroshi IWATA,  Satoshi OHTAKE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2010/6/18
[Paper #]DC2010-8
A Class of Partial Thru Testable Sequential Circuits with Multiplexers

Nobuya OKA,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2010/6/18
[Paper #]DC2010-9
A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths

Yuki YOSHIKAWA,  Shun MARUYA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2010/6/18
[Paper #]DC2010-10
A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults

Yun Chen,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  

[Date]2010/6/18
[Paper #]DC2010-11
Note on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique

Masayuki Arai,  Yoshihiro Tabata,  Kazuhiko Iwasaki,  

[Date]2010/6/18
[Paper #]DC2010-12
An I/O Sequence Slicing Method for Post-silicon Debugging

Yeonbok LEE,  Takeshi MATSUMOTO,  Masahiro FUJITA,  

[Date]2010/6/18
[Paper #]DC2010-13
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[Date]2010/6/18
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