Information and Systems-Dependable Computing(Date:2009/11/25)



[Paper #]


[Paper #]
Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis

Keisuke INOUE,  Mineo KANEKO,  

[Paper #]VLD2009-43,DC2009-30
A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System

Kazuhiro ITO,  Hyun-Joon KIM,  

[Paper #]VLD2009-44,DC2009-31
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI

Hidekazu SETO,  Kazuhito ITO,  

[Paper #]VLD2009-45,DC2009-32
Evaluation of Hardware/Software Partitioning Method with Consideration of Timing

Junya Matsunaga,  Michiaki Muraoka,  

[Paper #]VLD2009-46,DC2009-33
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications


[Paper #]VLD2009-47,DC2009-34
Simulation-Based Bus Width Optimization for Two-Level Caches

Shinta WATANABE,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Paper #]VLD2009-48,DC2009-35
An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits

Yusuke AKAMINE,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Paper #]VLD2009-49,DC2009-36
BILBO Register with Soft Error Detection Function

Masahiro SUGASAWA,  Kazuteru NAMBA,  Hideo ITO,  

[Paper #]VLD2009-50,DC2009-37
An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism

Tomohide NAGAI,  Masashi IMAI,  Takashi NANYA,  

[Paper #]VLD2009-51,DC2009-38
A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures

Yuma ITO,  Masayoshi YOSHIMURA,  Hiroto YASUURA,  

[Paper #]VLD2009-52,DC2009-39
Detection of Fault Candidate portions by DEF data Visualization

Kazuaki KISHI,  Masaru SANADA,  

[Paper #]VLD2009-53,DC2009-40
A Yield Model with Testability and Repairability

Yujiro AMANO,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Paper #]VLD2009-54,DC2009-41
Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity

Isao BEPPU,  Kohei MIYASE,  Yuta YAMATO,  Xiaoqing WEN,  Seiji KAJIHARA,  

[Paper #]VLD2009-55,DC2009-42
Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array

Shinya KUBOTA,  Minoru WATANABE,  

[Paper #]VLD2009-56,DC2009-43
A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter

Kimio SHIBATA,  Cong-Kha PHAM,  

[Paper #]VLD2009-57,DC2009-44
A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk

Masayuki KOBAYASHI,  Wataru SENTO,  Masahiko TOYONAGA,  Michiaki MURAOKA,  

[Paper #]VLD2009-58,DC2009-45
Increasing Yield Using Partially-Programmable Circuits

Shigeru YAMASHITA,  Hiroaki YOSHIDA,  Masahiro FUJITA,  

[Paper #]VLD2009-59,DC2009-46
Transistor-Array-Based OPAMP Layout and its Evaluation

Arisa KAWAZOE,  Toru FUJIMURA,  Shigetoshi NAKATAKE,  

[Paper #]VLD2009-60,DC2009-47
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