Information and Systems-Dependable Computing(Date:2008/02/01)

Presentation
表紙

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[Date]2008/2/1
[Paper #]
目次

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[Date]2008/2/1
[Paper #]
ESD/Latch up Failure Analysis of CMOS LSI : Failure Mode Analysis with Actual Data

Hideo KOHINATA,  Masayuki ARAI,  Satoshi FUKUMOTO,  

[Date]2008/2/1
[Paper #]DC2007-67
Fault Diagnosis for Dynamic Open Faults with Considering Adjacent Lines

Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Takashi AIKYO,  Syuhei KADOYAMA,  Tetsuya WATANABE,  Yuzo TAKAMATSU,  Toshiyuki TSUTUSMI,  Kouji YAMAZAKI,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  

[Date]2008/2/1
[Paper #]DC2007-68
Diagnostic Test Generation for Transition Faults

Takashi AIKYO,  Yoshinobu HIGAMI,  Hiroshi TAKAHASHI,  Toru KIKKAWA,  Yuzo TAKAMATSU,  

[Date]2008/2/1
[Paper #]DC2007-69
A Test Generation for Full Scan Circuit Using Multi Cycle Capture Test

Yusho OMORI,  Hiroshi OGAWA,  Toshinori HOSOKAWA,  Masayoshi YOSHIMURA,  Kouji YAMAZAKI,  

[Date]2008/2/1
[Paper #]DC2007-70
A variable n-detection test generation method to increase fault sensitization coverage and evaluation of its test quality

Takeshi TOMITA,  Toshinori HOSOKAWA,  Koji YAMAZAKI,  

[Date]2008/2/1
[Paper #]DC2007-71
Note on Test Power Reduction for Scan-Based Hybrid BIST

Akifumi SUTO,  Masayuki ARAI,  Kazuhiko IWASAKI,  

[Date]2008/2/1
[Paper #]DC2007-72
Secure Scan Design Based on Balanced Structure

Muneo HASEGAWA,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2008/2/1
[Paper #]DC2007-73
Fault Secure Property for Soft Error on FPGA Using Two-Rail Logic

Takehiro MIURA,  Kazuteru NAMBA,  Hideo ITO,  

[Date]2008/2/1
[Paper #]DC2007-74
Synthesis of Fault Secure Datapaths with DFG Restructuring

Hirotaka SHIOMICHI,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2008/2/1
[Paper #]DC2007-75
An evaluation of encryption LSI testability against scan based attack

Yuma ITO,  Masayoshi YOSHIMURA,  Hiroto YASUURA,  

[Date]2008/2/1
[Paper #]DC2007-76
RTL False Path Identification Using High Level Synthesis Information

Naotsugu IKEDA,  Satoshi OHTAKE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2008/2/1
[Paper #]DC2007-77
A Test Generation Method for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint

Ryoichi INOUE,  Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2008/2/1
[Paper #]DC2007-78
Comparison of exact solutions and greedy solutions in static test compaction

Kei Yagisawa,  Koji Yamazaki,  Toshinori Hosokawa,  Hisao Tamaki,  

[Date]2008/2/1
[Paper #]DC2007-79
Current dissipation of Test pattern generators using ATPG vectors

Hidekazu Tsuchiya,  Takaya Abe,  Takeshi Asakawa,  

[Date]2008/2/1
[Paper #]DC2007-80
Note on Testing of RF Transmitter Considering Component Variation

Tatsuro ENDO,  Masayuki ARAI,  Kazuhiko IWASAKI,  

[Date]2008/2/1
[Paper #]DC2007-81
Fault Diagnosis of Analog Circuits by Using Multiple Transistors and Data Samplings

Jiro KATO,  Yukiya MIURA,  

[Date]2008/2/1
[Paper #]DC2007-82
A Self-Correction Method for Periodic Signals

Yukiya MIURA,  

[Date]2008/2/1
[Paper #]DC2007-83
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[Date]2008/2/1
[Paper #]
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