Information and Systems-Dependable Computing(Date:2007/03/09)

Presentation
表紙

,  

[Date]2007/3/9
[Paper #]
目次

,  

[Date]2007/3/9
[Paper #]
A Context Assignment Algorithm for Functional Modules with Timing Constraints on Dynamic Reconfigurable Processor

Tomoya KITANI,  Ryo NAKAHASHI,  Akio NAKATA,  Keiichi YASUMOTO,  Teruo HIGASHINO,  

[Date]2007/3/9
[Paper #]CPSY2006-85,DC2006-99
Secure Content Distribution System with Self Run-Time Partial Reconfiguration of an FPGA

Yohei HORI,  Hiroyuki YOKOYAMA,  Hirofurni SAKANE,  Kenji TODA,  

[Date]2007/3/9
[Paper #]CPSY2006-86,DC2006-100
Parallelization with area partitioning for FPGA placement algorithm base on SA

Tomohiro OKAJIMA,  Yuji ARIUCHI,  Morihiro KUGA,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2007/3/9
[Paper #]CPSY2006-87,DC2006-101
A UML Profile for analyzing the external environments of embedded systems

Toshiki Seto,  Hirotoshi Kanagawa,  Naoyasu Ubayashi,  Takeshi Sumi,  Masayuki Hirayama,  

[Date]2007/3/9
[Paper #]CPSY2006-88,DC2006-102
A Hardware Design Method Using Semi-Programmable Reconfigurable Processor

Akira YAMAWAKI,  Masahiko IWANE,  

[Date]2007/3/9
[Paper #]CPSY2006-89,DC2006-103
Porting and Performance Evaluation of Linux Kernel 2.6.14 to ARM7TDMI

Yu KANEKO,  Masahiro ISHIYAMA,  

[Date]2007/3/9
[Paper #]CPSY2006-90,DC2006-104
Soft Real-Time Scheduling that Bounds Deadline Tardiness on Prioritized Simultaneous Multithreading

Akira TAKEDA,  Kenji FUNAOKA,  Shinpei KATO,  Nobuyuki YAMASAKI,  

[Date]2007/3/9
[Paper #]CPSY2006-91,DC2006-105
A Dynamic-Priority Scheduling Algorithm for Improving the Schedulability on Multiprocessors

Shinpei KATO,  Nobuyuki YAMASAKI,  

[Date]2007/3/9
[Paper #]CPSY2006-92,,DC2006-106
Frequency Scaling in Real-Time Scheduling on Multiprocessors

Kenji FUNAOKA,  Shinpei KATO,  Nobuyuki YAMASAKI,  

[Date]2007/3/9
[Paper #]CPSY2006-93,DC2006-107
Equivalence Checking of Loop Optimizations in C Programs without Loop Unrolling

Takeshi MATSUMOTO,  Kenshu SETO,  Masahiro FUJITA,  

[Date]2007/3/9
[Paper #]CPSY2006-94,DC2006-108
Efficient Translation of Logic Circuits to CNF Formulae with BDD for Acceralating SAT-based Formal Verification

Kazuhiro NAKAMURA,  Tomohiro NARUSE,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2007/3/9
[Paper #]CPSY2006-95,DC2006-109
Acceleration of Prototyping Design Verification Using Circuit Modification

Keita INOUE,  Xing WEIJIE,  Shinji KIMURA,  

[Date]2007/3/9
[Paper #]CPSY2006-96,DC2006-110
複写される方へ

,  

[Date]2007/3/9
[Paper #]
奥付

,  

[Date]2007/3/9
[Paper #]