Information and Systems-Dependable Computing(Date:2006/11/21)

Presentation
表紙

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[Date]2006/11/21
[Paper #]
目次

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[Date]2006/11/21
[Paper #]
A methodology of generating verification scenarios from specification

Ryosuke OISHI,  Akio MATSUDA,  Hiroaki IWASHITA,  Koichiro TAKAYAMA,  

[Date]2006/11/21
[Paper #]VLD2006-51,DC2006-38
Equivalence Checking using a Decidable Subclass of First-Order-Logic under Equivalence Constraints

Hiroaki KOZAWA,  Kiyoharu HAMAGUCHI,  Toshinobu KASHIWABARA,  

[Date]2006/11/21
[Paper #]VLD2006-52,DC2006-39
Bounded Model Checking for Assertions including Dynamic Local Variables

Sho TAKEUCHI,  Kiyoharu HAMAGUCHI,  Tosinobu KASHIWABARA,  

[Date]2006/11/21
[Paper #]VLD2006-53,DC2006-40
Formal Verification Method for Arithmetic Circuits and Its Evaluation

Yuki WATANABE,  Naofumi HOMMA,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]2006/11/21
[Paper #]VLD2006-54,DC2006-41
A Method of Test Plan Generation in Hierarchical Test Based on Balanced Structure

Yudai KAWAHARA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2006/11/21
[Paper #]VLD2006-55,DC2006-42
Test Compression/Decompression with the Decoding Function in Multimedia Cores

Yukinori SETOHARA,  Yusuke NAKASHIMA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2006/11/21
[Paper #]VLD2006-56,DC2006-43
Test relaxation for N-detection test patterns in broad-side delay testing

Kenjiro Taniguchi,  Kohei Miyase,  Seiji Kajihara,  Xiaoqing Wen,  

[Date]2006/11/21
[Paper #]VLD2006-57,DC2006-44
Decision Diagram Data Structure to Represent Quantum Circuit

Shigeru YAMASHITA,  D. MICHAEL MILLER,  

[Date]2006/11/21
[Paper #]VLD2006-58,DC2006-45
Depth-Optimum and Area-Optimal Technology Mapping for LUT-based FPGAs

Taiga TAKATA,  Yusuke MATSUNAGA,  

[Date]2006/11/21
[Paper #]VLD2006-59,DC2006-46
Asymmetric Slope Differential Logic with High-Speed and Low-Power Operation Modes

Masao MORIMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2006/11/21
[Paper #]VLD2006-60,DC2006-47
Test Scheduling for SoGs with Built-In Self-Repairable Memory Cores

Yusuke FUKUDA,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2006/11/21
[Paper #]VLD2006-61,DC2006-48
A Self-Test of Dynamically Reconfigurable Processors

Takashi FUJII,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2006/11/21
[Paper #]VLD2006-62,DC2006-49
Proposal of a Behavioral Synthesis Method for Asynchronous Circuits in Budled-data Implementation

Naohiro HAMADA,  Takao KONISHI,  Hiroshi SAITO,  Tomohiro YONEDA,  Takashi NANYA,  

[Date]2006/11/21
[Paper #]VLD2006-63,DC2006-50
A Basic Study on Datapath Synthesis Considering Delay Variation

Keisuke INOUE,  Mineo KANEKO,  Tsuyoshi IWAGAKI,  

[Date]2006/11/21
[Paper #]VLD2006-64,DC2006-51
Computational Complexity of Simultaneous Optimization of Control Schedule and Skew in Datapath Synthesis

Takayuki OBATA,  Mineo KANEKO,  

[Date]2006/11/21
[Paper #]VLD2006-65,DC2006-52
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[Date]2006/11/21
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[Date]2006/11/21
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[Date]2006/11/21
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