Information and Systems-Dependable Computing(Date:2006/02/10)

Presentation
表紙

,  

[Date]2006/2/10
[Paper #]
目次

,  

[Date]2006/2/10
[Paper #]
A Register Binding Method in High Level Synthesis for Strong Testability

Go HANDA,  Naoya TAKEUCHI,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2006/2/10
[Paper #]DC2005-72
DFT of Instruction-Based Self-Test for Non-pipelined Processors

Nobuhiro YAMAGATA,  Masato NAKAZATO,  Kazuko KAMBE,  Tomokazu YONEDA,  Satoshi OHTAKE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2006/2/10
[Paper #]DC2005-73
Fault Independent/Dependent Test Methods for State-Observable FSMs

Ryoichi INOUE,  Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2006/2/10
[Paper #]DC2005-74
A Statistical Study on Fault Coverage of the Logic BIST with LFSR

Satoshi FUKUMOTO,  Harunobu KUROKAWA,  Masayuki ARAI,  Kazuhiko IWASAKI,  

[Date]2006/2/10
[Paper #]DC2005-75
Open Fault Model with Considering Adjacent Lines and its Fault Diagnosis

Syuhei KADOYAMA,  Kiyoshi TAKECHI,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Kouji YAMAZAKI,  Yuzo TAKAMATSU,  

[Date]2006/2/10
[Paper #]DC2005-76
Implementation and its evaluation of an autonomous cascaded DB replication method

Hiroshi KUROSE,  Minoru NAKAZAWA,  Shimmi HATTORI,  

[Date]2006/2/10
[Paper #]DC2005-77
Development and Evaluation of a System for Facility Diagnosis of Rotating Machines

Yasuyuki Oguma,  Masahiro Tsunoyama,  Youichi Jinno,  Masayuki Ogawa,  Tatsuo Sato,  

[Date]2006/2/10
[Paper #]DC2005-78
A High-Level Memory Test Description Language for Dynamic Reconfigurable Memory Tester and Convertion to VHDL

Satoru MORIYA,  Takeshi YANASE,  Yukihiro IGUCHI,  Shuichi KAMEYAMA,  Hiromi SHIMADA,  

[Date]2006/2/10
[Paper #]DC2005-79
A New Class of Sequential Circuits with Acyclic Test Generation Complexity

Chia Yee Ooi,  

[Date]2006/2/10
[Paper #]DC2005-80
On generation of transition faults test patterns in consideration of the path length in broadside testing

Shohei MORISHIMA,  Akane TAKUMA,  Seiji KAJIHARA,  Xiaoqing WEN,  Toshiyuki MAEDA,  Shuji HAMADA,  Yasuo SATO,  

[Date]2006/2/10
[Paper #]DC2005-81
Proposal of a Clock Signal Generation/Detection Method Considering Crosstalk

Yukiya MIURA,  

[Date]2006/2/10
[Paper #]DC2005-82
Speed-up method of delay sensitized path calculation in transition delay test

Shyuji HAMADA,  Toshiyuki MAEDA,  Atsuo TAKATORI,  Yasuyuki NOZDUYAMA,  Yasuo SATO,  

[Date]2006/2/10
[Paper #]DC2005-83
複写される方へ

,  

[Date]2006/2/10
[Paper #]
奥付

,  

[Date]2006/2/10
[Paper #]