Information and Systems-Dependable Computing(Date:2005/11/23)

Presentation
表紙

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[Date]2005/11/23
[Paper #]
目次

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[Date]2005/11/23
[Paper #]
Layout CAD and DFM : Beginning and Maturity

Takashi Mitsuhashi,  

[Date]2005/11/23
[Paper #]VLD2005-54,ICD2005-149,DC2005-31
40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS technology

Kouichi Kanda,  Daisuke Yamazaki,  Takuji Yamamoto,  Minoru Horinaka,  Junji Ogawa,  Hirotaka Tamura,  Hiroyuki Onodera,  

[Date]2005/11/23
[Paper #]VLD2005-55,ICD2005-150,DC2005-32
Enhancement of an Angular Position Error Measurement Circuit for Rotary Encoders

Teruo Tamama,  Masahiro Sugiura,  Tadashi Masuda,  

[Date]2005/11/23
[Paper #]VLD2005-56,ICD2005-151,DC2005-33
Low Power Design for IEEE 802.11 WLAN at the Medium Access Control Layer

EL Bourichi Adil,  Hiroto Yasuura,  

[Date]2005/11/23
[Paper #]VLD2005-57,ICD2005-152,DC2005-34
Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition

Masao MORIMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2005/11/23
[Paper #]VLD2005-58,ICD2005-153,DC2005-35
A Discussion about Timing Signal Design Considering Characteristics of Delay Variations

Masashi IMAI,  Kouichi WATANABE,  Masaaki KONDO,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2005/11/23
[Paper #]VLD2005-59,ICD2005-154,DC2005-36
Design of High Performance and Low Power Arithmetic Circuits Considering Bit Delay Variation

Kouichi WATANABE,  Masashi IMAI,  Masaaki KONDO,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2005/11/23
[Paper #]VLD2005-60,ICD2005-155,DC2005-37
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[Date]2005/11/23
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[Date]2005/11/23
[Paper #]
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[Date]2005/11/23
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