Information and Systems-Dependable Computing(Date:2005/02/11)

Presentation
表紙

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[Date]2005/2/11
[Paper #]
目次

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[Date]2005/2/11
[Paper #]
Design for Partially Strong Testability of Data Paths to Guarantee Complete Fault Efficiency

Hiroyuki IWATA,  Tomokazu YONEDA,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-92
A Functional Test Method for State-Observable Incompletely Specified FSMs

Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-93
Design for Hierarchical Testability for Reducing Hold Controls

Naoki OKAMOTO,  Hideyuki ICHIHARA,  Tomoo INOUE,  Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-94
1 Multiple Primary Output Detection Test Pattern Generation

Daisuke NAKAZATO,  Toshinori HOSOKAWA,  Koji YAMAZAKI,  Tsukasa ISHIGURO,  Hiroshi DATE,  

[Date]2005/2/11
[Paper #]DC2004-95
Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation

Tsuyoshi IWAGAKI,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-96
Acceleration of Test Generation for Sequential Circuit Using Knowledge Obtained from Synthesis for Testability

Masato NAKAZATO,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-97
A Note on X-Masking Probability of Convolutional Compactors

Masayuki ARAI,  Satoshi FUKUMOTO,  Kazuhiko IWASAKI,  

[Date]2005/2/11
[Paper #]DC2004-98
Bridging Fault Diagnosis based on Detecting/Undetecting Information of Ambiguous Test Set

Kazuki KURIYAMA,  Takahiro NISHIYAMA,  Yoshinobu HIGAMI,  Kouji YAMAZAKI,  Hiroshi TAKAHASHI,  Yuzo TAKAMATSU,  

[Date]2005/2/11
[Paper #]DC2004-99
Diagnosis for Open Faults Based on Detecting/Un-detecting Information on Ambiguous Test Set

Kiyoshi TAKECHI,  Yuich SATO,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Kouji YAMAZAKI,  Yuzo TAKAMATSU,  

[Date]2005/2/11
[Paper #]DC2004-100
Scheduling Analysis of Soft Reeal-Time Systems using Timed Automata

Satoshi YAMANE,  

[Date]2005/2/11
[Paper #]DC2004-101
A Reconfigurable Union Wrapper for SoC Test Scheduling

Masahiro IMANISHI,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-102
Test Scheduling for Multi-clock Domain SoC with Power Constraints

Kimihiko MASUDA,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2005/2/11
[Paper #]DC2004-103
Research to Effectiveness of N-detection Test Sets for Fault Diagnosis

Tsukasa ISHIGURO,  Daisuke NAKAZATO,  Koji YAMAZAKI,  Toshinori HOSOKAWA,  

[Date]2005/2/11
[Paper #]DC2004-104
Diagnosis for Open Faults by Using Erroneous Path Tracing Based on Detecting/Un-detecting Information

Koji YAMAZAKI,  Yoshinobu HIGAMI,  Hiroshi TAKAHASHI,  Yuzo TAKAMATSU,  

[Date]2005/2/11
[Paper #]DC2004-105
A Method for Diagnosing Multiple Fault Models based on Detecting/un-detecting Information

Akane YAMASAKI,  Tetsuya SEIYAMA,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Kouji YAMAZAKI,  Yuzo TAKAMATSU,  

[Date]2005/2/11
[Paper #]DC2004-106
Test Compaction for Path Delay Faults in Deep Submicron LSIs

Seiji Kajihara,  Masayasu Fukunaga,  Xiaoqing Wen,  Toshiyuki Maeda,  Shuji Hamada,  Yasuo Sato,  

[Date]2005/2/11
[Paper #]DC2004-107
Statistical Delay Quality Model for Defect Level Estimation

Yasuo Sato,  Shuji Hamada,  Toshiyuki Maeda,  Atsuo Takatori,  Seiji Kajihara,  

[Date]2005/2/11
[Paper #]DC2004-108
Interconnect Open Detection by Ramp Voltage Application

Yukiya MIURA,  

[Date]2005/2/11
[Paper #]DC2004-109
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