Information and Systems-Computer Systems(Date:2022/01/24)

Presentation
FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation

Kaoru Yamamoto(TUS),  Takayuki Kawahara(TUS),  

[Date]2022-01-24
[Paper #]VLD2021-53,CPSY2021-22,RECONF2021-61
Accelerating Deep Neural Networks on Edge Devices by Knowledge Distillation and Layer Pruning

Yuki Ichikawa(Titech),  Akira Jinguji(Titech),  Ryosuke Kuramochi(Titech),  Hiroki Nakahara(Titech),  

[Date]2022-01-24
[Paper #]VLD2021-58,CPSY2021-27,RECONF2021-66
Addition of DPU Training Function by Tail Layer Training

Yuki Takashima(Tokyo Tech),  Akira Jinguji(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  

[Date]2022-01-24
[Paper #]VLD2021-59,CPSY2021-28,RECONF2021-67
A study of an accelerator for CNN inference on FPGA clusters

Rintaro Sakai(Kumamoto Univ. /R-CSS),  Yasuhiro Nakahara(Kumamoto Univ. /R-CCS),  Kentaro Sano(R-CCS),  Masahiro Iida(Kumamoto Univ. /R-CCS),  

[Date]2022-01-24
[Paper #]VLD2021-60,CPSY2021-29,RECONF2021-68
Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer

Takuya Ando(Kwansei Gakuin Univ.),  Yugo Ishii(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  Hiroyuki Tomiyama(Ritsumeikan Univ.),  Hiroyuki Kanbara(ASTEM RI/KYOTO),  

[Date]2022-01-24
[Paper #]VLD2021-51,CPSY2021-20,RECONF2021-59
Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems

Yukino Shinohara(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  

[Date]2022-01-24
[Paper #]VLD2021-52,CPSY2021-21,RECONF2021-60
Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers

Takahiro Morii(Gunma Univ.),  Yuuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2022-01-24
[Paper #]VLD2021-50,CPSY2021-19,RECONF2021-58
IMAX2を用いた高効率な疎行列-疎行列積の実装

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[Date]2022-01-24
[Paper #]VLD2021-56,CPSY2021-25,RECONF2021-64
Multi-spin-flip method for Ising machines and its application

Tatsuhiko Shirai(Waseda Univ.),  Nozomu Tagawa(Waseda Univ.),  

[Date]2022-01-24
[Paper #]VLD2021-54,CPSY2021-23,RECONF2021-62
Implementation of a RISC-V SMT Core in Virtual Engine Architecture

Hidetaro Tanaka(TUAT),  Tomoaki Tanaka(TUAT),  Keita Nagaoka(TUAT),  Ryosuke Higashi(TUAT),  Tsutomu Sekibe(ArchiTek),  Shuichi Takada(ArchiTek),  Hironori Nakajo(TUAT),  

[Date]2022-01-24
[Paper #]VLD2021-57,CPSY2021-26,RECONF2021-65
Ternarizing Deep Spiking Neural Network

Man Wu(NAIST),  Yirong Kan(NAIST),  Van_Tinh Nguyen(NAIST),  Renyuan Zhang(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2022-01-24
[Paper #]VLD2021-61,CPSY2021-30,RECONF2021-69
Study on a Correlation Controlling Method to Realize Correlation-used Calculations Sequentially in Stochastic Computing

Shu Zhang(Ritsumeikan Univ.),  Shigeru Yamashita(Ritsumeikan Univ.),  

[Date]2022-01-24
[Paper #]VLD2021-49,CPSY2021-18,RECONF2021-57
[Invited Talk] A Challenge of Research, Development, Manufacturing, and Marketing of Quantum Computing Control Systems

Takefumi Miyoshi(QuEL, Inc./e-trees.Japan, Inc./Osaka Univ.),  

[Date]2022-01-24
[Paper #]VLD2021-55,CPSY2021-24,RECONF2021-63
A Light-Weight Machine Learning based Packet Routing using Online Sequential Learning

Kenji Nemoto(Keio Univ.),  Masaki Furukawa(Keio Univ.),  Hirohisa Watanabe(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-66,CPSY2021-35,RECONF2021-74
An Accuracy-Aware Data Size Reduction Method of 3D Lidar SLAM

Ryuto Kojima(Keio Univ.),  Keisuke Sugiura(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-63,CPSY2021-32,RECONF2021-71
GPU acceleration of algorithm for minimal distance approximate calculation between two objects

Masumi Fukuta(NDA),  Takakazu Kurokawa(NDA),  Takashi Matsubara(NDA),  Keisuke Iwai(NDA),  

[Date]2022-01-25
[Paper #]VLD2021-62,CPSY2021-31,RECONF2021-70
FPGA Implementation of Radar Imaging for Walk-Through Security Screening System

Tatsuya Sumiya(NEC),  Yuki Kobayashi(NEC),  Masayuki Ariyoshi(NEC),  

[Date]2022-01-25
[Paper #]VLD2021-64,CPSY2021-33,RECONF2021-72
An Implementation of a Real-time Stereo Matching System on FPGA

Kaijie Wei(Keio Univ.),  Yuki Kuno(Marelli Corp.),  Masatoshi Arai(Saitama Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-65,CPSY2021-34,RECONF2021-73
Hard-to-Detect Hardware Trojan Attack Exploiting Coherence Control Mechanisms

Yoshiya Shikama(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-75,CPSY2021-44,RECONF2021-83
Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC

Boma Adhi(R-CCS),  Carlos Cortes(R-CCS),  Yiyu Tan(R-CCS),  Takuya Kojima(Tokyo Univ.),  Artur Podobas(KTH),  Kentaro Sano(R-CCS),  

[Date]2022-01-25
[Paper #]VLD2021-71,CPSY2021-40,RECONF2021-79
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