Information and Systems-Computer Systems(Date:2019/01/30)

Presentation
Design and implementation of FPGA measurement feedback system in Coherent Ising Machine

Toshimori Honjo(NTT),  Takahiro Inagaki(NTT),  Kensuke Inaba(NTT),  Takuya Ikuta(NTT),  Hiroki Takesue(NTT),  

[Date]2019-01-30
[Paper #]VLD2018-78,CPSY2018-88,RECONF2018-52
On Delay Optimization for Improving General Synchronous Performance

Eijiro Sassa(Tokyo Tech),  Shimpei Sato(Tokyo Tech),  Atsushi Takahashi(Tokyo Tech),  

[Date]2019-01-30
[Paper #]VLD2018-72,CPSY2018-82,RECONF2018-46
Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm

Masaki Ogino(Gunma Univ.),  Yuki Tanaka(Gunma Univ.),  Shugang Wei(Gunma Univ.),  

[Date]2019-01-30
[Paper #]VLD2018-73,CPSY2018-83,RECONF2018-47
Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation

Masayuki Shimoda(titech),  Youki Sada(titech),  Hiroki Nakahara(titech),  

[Date]2019-01-30
[Paper #]VLD2018-76,CPSY2018-86,RECONF2018-50
[Invited Talk] Large Scale PC Cluster Technologies

Kohta Nakashima(Fujitsu lab.),  

[Date]2019-01-30
[Paper #]VLD2018-81,CPSY2018-91,RECONF2018-55
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults

Peikun Wang(UTokyo),  Amir Masoud Gharehbaghi(UTokyo),  Masahiro Fujita(UTokyo),  

[Date]2019-01-30
[Paper #]VLD2018-74,CPSY2018-84,RECONF2018-48
A CNN with a Noise Addition for Efficient Implementation on an FPGA

Atsuki Munakata(Tokyo Tech),  Shimpei Satou(Tokyo Tech),  Hiroki Nakahara(Tokyo Tech),  

[Date]2019-01-30
[Paper #]VLD2018-75,CPSY2018-85,RECONF2018-49
Study of stacked full adder circuit with fabrication technology of 3D flash memory

Fumiya Suzuki(Shonan Inst. of Tech.),  Sigeyoshi Watanabe(Shonan Inst. of Tech.),  

[Date]2019-01-30
[Paper #]VLD2018-77,CPSY2018-87,RECONF2018-51
Implementation of Image Processing Algorithm Aiming for Autonomous Car Using FPGA

Koki Honda(Keio Univ.),  Wei Kaije(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2019-01-30
[Paper #]VLD2018-80,CPSY2018-90,RECONF2018-54
An integrated development platform of FPGA for ROS-based autonomous mobile robot

Sou Tamura(Kyoto Univ),  Yasuhiro Nitta(Kyoto Univ),  Hideki Takase(Kyoto Univ),  Kazuyoshi Takagi(Kyoto Univ),  Naofumi Takagi(Kyoto Univ),  

[Date]2019-01-30
[Paper #]VLD2018-79,CPSY2018-89,RECONF2018-53
A Deduplication Mechanism for Effectively-once Semantics Using FPGA NIC

Koji Suzuki(Keio Univ.),  Koya Mitsuzuka(Keio Univ.),  Takuma Iwata(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2019-01-31
[Paper #]VLD2018-83,CPSY2018-93,RECONF2018-57
異デバイス間でのPCIe通信を実現するOpenCL対応FPGAモジュールの提案と検証

Ryohei Kobayashi,  Norihisa Fujita,  Yoshiki Yamaguchi,  Taisuke Boku,  

[Date]2019-01-31
[Paper #]VLD2018-89,CPSY2018-99,RECONF2018-63
A Case for Unsupervised Abnormal Behavior Detection Using Multiple Online Sequential Learning Cores

Rei Ito(Keio Univ),  Mineto Tsukada(Keio Univ),  Masaaki Kondo(Univ Tokyo),  Hiroki Matsutani(Keio Univ),  

[Date]2019-01-31
[Paper #]VLD2018-85,CPSY2018-95,RECONF2018-59
データフロー型計算アプリケーション用DMACの高位合成による自動設計

Tomohiro Kida(Nagasaki Univ.),  Yuichi Kawamata(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kentaro Sano(RIKEN),  

[Date]2019-01-31
[Paper #]VLD2018-87,CPSY2018-97,RECONF2018-61
FPGA上での部分再構成を使用したストリーム向けクロスバの実装と検証

Yuichi Kawamata(Nagasaki Univ.),  Tomohiro Kida(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kentaro Sano(RIKEN),  

[Date]2019-01-31
[Paper #]VLD2018-90,CPSY2018-100,RECONF2018-64
非整列ストリームデータ処理向けマルチコアプロセッサシステムの検討と評価

Takefumi Miyoshi(TOYOTA ITC),  

[Date]2019-01-31
[Paper #]VLD2018-91,CPSY2018-101,RECONF2018-65
Area and Performance Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core

Tomoya Itsubo(Keio Univ.),  Mineto Tsukada(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2019-01-31
[Paper #]VLD2018-86,CPSY2018-96,RECONF2018-60
Preliminary evaluation of special instruction implementation methods by high level synthesis

Ryodai Iwamoto(TUT),  Naoki Fujieda(TUT),  Shuichi Ichikawa(TUT),  Joji Sakamoto(TUT),  

[Date]2019-01-31
[Paper #]VLD2018-88,CPSY2018-98,RECONF2018-62
The Evaluation of Partial Reconfiguration for FiCSW

Miho Yamakura(Keio Univ.),  Keita Azegami(Keio Univ.),  Kazusa Musha(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2019-01-31
[Paper #]VLD2018-82,CPSY2018-92,RECONF2018-56
An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card

Takaaki Miyajima(RIKEN),  Tomohiro Ueno(RIKEN),  Kentaro Sano(RIKEN),  

[Date]2019-01-31
[Paper #]VLD2018-92,CPSY2018-102,RECONF2018-66
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