Information and Systems-Computer Systems(Date:2015/04/17)

Presentation
3D Shared Bus Architecture Using Inductive-Coupling Interconnect

Akio Nomura(Keio Univ.),  Yu Fujita(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-4,DC2015-4
[Special Invited Talk] On Hardware for high-speed pattern matching

Tsutomu Sasao(Meiji Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-11,DC2015-11
A Case Study on Prototyping Cloud based IoT devices

Minoru Uehara(Toyo Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-13,DC2015-13
A Proposal of Time-Lag-Less n-Fault-Tolerant Control System

Hitoshi Iwai(*),  

[Date]2015-04-17
[Paper #]CPSY2015-3,DC2015-3
Off-loading to PEACH2 of Gravitational Calculation

Chiharu Tsuruta(Keio univ.),  Takuya Kuhara(Keio univ.),  Miki Yohei(Univ. of Tsukuba),  Hideharu Amano(Keio univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-2,DC2015-2
A study of processor architecture suited for intelligent sensing system

Hiroki Hihara(Univ. of Tokyo),  Akira Iwasaki(Univ. of Tokyo),  Masanori Hashimoto(Osaka Univ./JST CREST),  Hiroyuki Ochi(Rits/JST CREST),  Yukio Mitsuyama(KUT/JST CREST),  Hidetoshi Onodera(Kyoto Univ./JST CREST),  Hiroyuki Kanbara(ASTEM/JST CREST),  Kazutoshi Wakabayashi(NEC/JST CREST),  Takashi Takenaka(NEC/JST CREST),  Takashi Takenaka(NEC/JST CREST),  Hiromitsu Hada(NEC/JST CREST),  Munehiro Tada(NEC/JST CREST),  

[Date]2015-04-17
[Paper #]CPSY2015-8,DC2015-8
An IP-NoC Translator for Connecting NoCs and Internet

Naoaki Kashiwagi(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-6,DC2015-6
Frequency Domain aware Power Analysis based on Two Steps Hierarchal Alignment Method

Yusuke Nozaki(Meijo Univ.),  Masaya Yoshikawa(Meijo Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-14,DC2015-14
Parallel Processor Architecture based on Small World Connection

Hideki Mori(Meiji Univ.),  Minoru Uehara(Toyo Univ.),  Katsuyoshi Matsumoto(Toyo Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-10,DC2015-10
CGRA in Cache for Graph Applications

Shohei Takeuchi(NAIST),  Thi Hong Tran(NAIST),  Shinya Takamaeda(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2015-04-17
[Paper #]CPSY2015-7,DC2015-7
Near Memory Processing Architecture for High Performance Atypical Applications

Tadahiro Edamoto(NAIST),  Thi Hong Tran(NAIST),  Shinya Takamaeda(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2015-04-17
[Paper #]CPSY2015-9,DC2015-9
Prototyping of GPS-based Item Finder System

Soichiro Kanagawa(NAIST),  Thi Hong Tran(NAIST),  Shinya Takamaeda(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2015-04-17
[Paper #]CPSY2015-15,DC2015-15
Design and Implementation of FPGA-based Sorting Accelerator

Ryohei Kobayashi(Tokyo Tech),  Kenji Kise(Tokyo Tech),  

[Date]2015-04-17
[Paper #]CPSY2015-5,DC2015-5
Redundant Configuration on FPGA with Rejuvenation for Real Time Applications

Aromhack Saysanasongkham(Tokyo Metropolitan Univ.),  Satoshi Fukumoto(Tokyo Metropolitan Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-1,DC2015-1
A parallel-operation-oriented FPGA architecture

Takumi Fujimori(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2015-04-17
[Paper #]CPSY2015-12,DC2015-12