Information and Systems-Computer Systems(Date:2014/11/19)

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[Date]2014/11/19
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目次

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[Date]2014/11/19
[Paper #]
Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing

Yoshifumi FUJIKAWA,  Tetsuro HOMMURA,  Tadayuki MATSUMURA,  

[Date]2014/11/19
[Paper #]CPSY2014-72
A Large Graph Segmentation Method for Triangle Counting

Tatsuhiro HIRANO,  Shinya TAKAMAEDA-YAMAZAKI,  Jun YAO,  Yasuhiko NAKASHIMA,  

[Date]2014/11/19
[Paper #]CPSY2014-73
Parallelization of Shortest Path Search on Various Platforms and Its Evaluation

Shuto KUREBAYASHI,  Shinya TAKAMAEDA-YAMAZAKI,  Jun YAO,  Yasuhiko NAKASHIMA,  

[Date]2014/11/19
[Paper #]CPSY2014-74
An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders

Hiroyuki YATAKA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2014/11/19
[Paper #]CPSY2014-75
A complex multiplier using two floating-point fused multiply-add unit

Yuhei TAKATA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2014/11/19
[Paper #]CPSY2014-76
Magnetic Resonance (MR) Safety of Implantable Medical Device : Current Status and Future Prospect

Kagayaki KURODA,  

[Date]2014/11/19
[Paper #]VLD2014-92,CPM2014-122,OCD2014-65,CPSY2014-77,DC2014-46,RECONF2014-40
Latest Development and Future Prospect of Mobile Display Technology

Yoshiharu NAKAJIMA,  

[Date]2014/11/19
[Paper #]VLD2014-93,CPM2014-123,ICD2014-66,CPSY2014-78,DC2014-47,RECONF2014-41
Scalable and Low Latency Structure for Castle of Chips

Hiroshi NAKAHARA,  Hiroki MATSUTANI,  Michihiro KOIBUCHI,  Hideharu AMANO,  

[Date]2014/11/19
[Paper #]CPSY2014-79
A Distributed Router Architecture using transparent latches for Network-on- Chips

Ryota YASUDO,  Hiroki MATSUTANI,  Michihiro KOIBUCHI,  Hideharu AMANO,  Tadao NAKAMURA,  

[Date]2014/11/19
[Paper #]CPSY2014-80
Implementation and Evaluation of An Accelerator based on Manymemory Network

Ryo SHIMIZU,  Masakazu TANOMOTO,  YAMAZAKI Shinya TAKAMAEDA,  Jun YAO,  Yasuhiko NAKASHIMA,  

[Date]2014/11/19
[Paper #]CPSY2014-81
Convolutional Neural Network Processing on An Accelerator based on Manymemory Network

Masakazu TANOMOTO,  Shinya TAKAMAEDA-YAMAZAKI,  Jun YAO,  Yasuhiko NAKASHIMA,  

[Date]2014/11/19
[Paper #]CPSY2014-82
Looking Back over My Researches on Flexible Hardware : Reconfigurable Systems and FPGAs

Toshinori SUEYOSHI,  

[Date]2014/11/19
[Paper #]CPSY2014-83
A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS(Invited)

Yasufumi Sakai,  Takayuki Shibasaki,  Takumi Danjo,  Hisakatsu Yamaguchi,  Toshihiko Mori,  Yoichi Koyanagi,  Hirotaka Tamura,  

[Date]2014/11/19
[Paper #]VLD2014-96,CPM2014-127,ICD2014-70,CPSY2014-84,DC2014-50,RECONF2014-45
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[Date]2014/11/19
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Reprographic Reproduction outside Japan

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[Date]2014/11/19
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奥付

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[Date]2014/11/19
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[Date]2014/11/19
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