Information and Systems-Computer Systems(Date:2014/01/21)

Presentation
表紙

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[Date]2014/1/21
[Paper #]
目次

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[Date]2014/1/21
[Paper #]
Design and Implementation of High-Level Synthesis Compiler for Stream Computation

Ryo ITO,  Hayato SUZUKI,  Ryotaro CHIBA,  Kentaro SANO,  Satoru YAMAMOTO,  

[Date]2014/1/21
[Paper #]VLD2013-102,CPSY2013-73,RECONF2013-56
A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs

Chikako MIURA,  Shinobu NAGAYAMA,  Shin'ichi WAKABAYASHI,  Masato INAGI,  

[Date]2014/1/21
[Paper #]VLD2013-103,CPSY2013-74,RECONF2013-57
Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench

Naru SUGIMOTO,  Keimei MIYAJIMA,  Takuya KUHARA,  Takuzi MITUISHI,  Hideharu AMANO,  

[Date]2014/1/21
[Paper #]VLD2013-104,CPSY2013-75,RECONF2013-58
A Discussion on Hardware Architecture of SIFT Algorithm for FPGAs Utilizing a High-Level Synthesis Tool

Naohisa ARAKAWA,  Lint MENG,  Tomonori IZUMI,  

[Date]2014/1/21
[Paper #]VLD2013-105,CPSY2013-76,RECONF2013-59
A Storing and Regenerating Signal Information in a Scalable Hardware System

Yusuke KATOH,  Daisuke WATANABE,  Hironori NAKAJO,  

[Date]2014/1/21
[Paper #]VLD2013-106,CPSY2013-77,RECONF2013-60
Hardware Expansion Protocol in a Scalable Hardware System

Daisuke WATANABE,  Yusuke KATOH,  Hironori NAKAJO,  

[Date]2014/1/21
[Paper #]VLD2013-107,CPSY2013-78,RECONF2013-61
A FPGA/GPU cooperation in nodes communication using PEACH2

Takuya KUHARA,  Takaaki MIYAJIMA,  Toshihiro HANAWA,  Hideharu AMANO,  Taisuke BOKU,  

[Date]2014/1/21
[Paper #]VLD2013-108,CPSY2013-79,RECONF2013-62
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption

Tomoya TASAKI,  Hiroto KAGOTANI,  Yuji SUGIYAMA,  

[Date]2014/1/21
[Paper #]VLD2013-109,CPSY2013-80,RECONF2013-63
Research on VLSI Circuits : From Solving Problem to Creating Future(Invited)

Tadahiro Kuroda,  

[Date]2014/1/21
[Paper #]VLD2013-110,CPSY2013-81,RECONF2013-64
The Improvement of Auto-Sharding in MongoDB with Priority-Chunk

Yasuhiro SATO,  Ryota KAWASHIMA,  Hiroshi MATSUO,  

[Date]2014/1/21
[Paper #]VLD2013-111,CPSY2013-82,RECONF2013-65
Improving the Preformance of Virtual Machine Live Migration by Ordering Memory Page Transfer on Access Pattern

Shintaro NAKAI,  Ryota KAWASHIMA,  Hiroshi MATSUO,  

[Date]2014/1/21
[Paper #]VLD2013-112,CPSY2013-83,RECONF2013-66
A Vertical Link On/Off Algorithm for Wireless 3-D NoCs

Go MATSUMURA,  Michihiro KOIBUCHI,  Hideharu AMANO,  Hiroki MATSUTANI,  

[Date]2014/1/21
[Paper #]VLD2013-113,CPSY2013-84,RECONF2013-67
A Case for Low-Power Networks using FSO and On/Off Links

Tomoya OZAKI,  Michihiro KOIBUCHI,  Hideharu AMANO,  Hiroki MATSUTANI,  

[Date]2014/1/21
[Paper #]VLD2013-114,CPSY2013-85,RECONF2013-68
A 3D FPGA-Array "Vocalise" and its communication system

Yusuke ATSUMARI,  Jiang LI,  Hiromasa KUBO,  Akihiro SORIMACHI,  Baku OGASAWARA,  Masatoshi SEKINE,  

[Date]2014/1/21
[Paper #]VLD2013-115,CPSY2013-86,RECONF2013-69
An Image Recognition System with Multi-Resolutional Feature Learning on the 3D FPGA-Array "Vocalise"

Baku OGASAWARA,  Satoru YOKOTA,  Jiang LI,  Yusuke ATSUMARI,  Hiromasa KUBO,  Masatoshi SEKINE,  

[Date]2014/1/21
[Paper #]VLD2013-116,VLD2013-116,RECONF2013-70
二重キャッシングによるMemcached高速化の提案(FPGA応用,FPGA応用及び一般)

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[Date]2014/1/21
[Paper #]VLD2013-117,CPSY2013-88,RECONF2013-71
A study on module allocation in multi-FPGA systems

Yusuke HIRAI,  Kazuaki NAKAZATO,  TALIP Mohamed Sofian bin ABU,  Mishra DIPIKARANI,  Hideharu AMANO,  Naoyuki FUJITA,  Yasunori OSANA,  

[Date]2014/1/21
[Paper #]VLD2013-118,CPSY2013-89,RECONF2013-72
An Experimental Bit-Parallel Solution to Accelerate Smith-Waterman Algorithm

Saori SUDO,  Masato YOSHIMI,  Hidetsugu IRIE,  Tsutomu YOSHINAGA,  

[Date]2014/1/21
[Paper #]VLD2013-119,CPSY2013-90,RECONF2013-73
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