Information and Systems-Computer Systems(Date:2013/01/09)

Presentation
表紙

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[Date]2013/1/9
[Paper #]
目次

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[Date]2013/1/9
[Paper #]
Architecture Evaluation of a Reconfigurable Device MPLD

Tomoya YAMASHITA,  Masato INAGI,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  Takashi ISHIGURO,  

[Date]2013/1/9
[Paper #]VLD2012-107,CPSY2012-56,RECONF2012-61
A Design Method of Network-on-Chip Architecture for FPGA

Hideki KATABAMI,  Hiroshi SAITO,  

[Date]2013/1/9
[Paper #]VLD2012-108,CPSY2012-57,RECONF2012-62
A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer

Yusuke IWAI,  Qian ZHAO,  Motoki AMAGASAKI,  Masahiro IIDA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2013/1/9
[Paper #]VLD2012-109,CPSY2012-58,RECONF2012-63
Performance Evaluation of Parametalized Data Compression Hardware for Floating-Point Data Stream

Tomohiro Ueno,  Yoshiaki Kono,  Kentaro Sano,  Satoru Yamamoto,  

[Date]2013/1/9
[Paper #]VLD2012-110,CPSY2012-59,RECONF2012-64
An Architecture for IPv6 Lookup Using Parallel Index Generation Units

Hiroki NAKAHARA,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2013/1/9
[Paper #]VLD2012-111,CPSY2012-60,RECONF2012-65
Implementation of a neural network for FPGA-based digital DC-DC converters

Yoshihiko YAMABE,  Masashi MOTOMURA,  Kentaro YAMASHITA,  Hidenori MARUTA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  Fujio KUROKAWA,  

[Date]2013/1/9
[Paper #]VLD2012-112,CPSY2012-61,RECONF2012-66
Challenges and Opportunities for Normally-Off Computing

Hiroshi NAKAMURA,  

[Date]2013/1/9
[Paper #]VLD2012-113,CPSY2012-62,RECONF2012-67
Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number

Takuya KOBAYASHI,  Kazuhiro MOTEGI,  Shugang WEI,  

[Date]2013/1/9
[Paper #]VLD2012-114,CPSY2012-63,RECONF2012-68
Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic

Junichi ASAOKA,  Yuki TANAKA,  Shugang WEI,  

[Date]2013/1/9
[Paper #]VLD2012-115,CPSY2012-64,RECONF2012-69
Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation

Makoto Miyauchi,  Masaru Kudo,  Kimiyoshi Usami,  

[Date]2013/1/9
[Paper #]VLD2012-116,CPSY2012-65,RECONF2012-70
Scaling the Size of Expressions in Random Testing of Arithmetic Optimization of C Compilers

Eriko NAGAI,  Atsushi HASHIMOTO,  Nagisa ISHIURA,  

[Date]2013/1/9
[Paper #]VLD2012-117,CPSY2012-66,RECONF2012-71
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor

Kensaku MATSUNAGA,  Hideharu AMANO,  Masaru KUDO,  Ryuichi SAKAMOTO,  Yuya OHTA,  Mitaro NAMIKI,  Nao KONISHI,  Kimiyoshi USAMI,  

[Date]2013/1/9
[Paper #]VLD2012-118,CPSY2012-67,RECONF2012-72
Speeding up Multiple Sections of Binary Code by Hardware Accelerator Tightly Coupled with CPU

SHUNSUKE Satake,  Nagisa ISHIURA,  SHIMPEI Tamura,  Hiroyuki TOMIYAMA,  Hiroyuki KANBARA,  

[Date]2013/1/9
[Paper #]VLD2012-119,CPSY2012-68,RECONF2012-73
Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide(SOTB)

Shinya AJIRO,  Masaru KUDO,  Kimiyoshi USAMI,  

[Date]2013/1/9
[Paper #]VLD2012-120,CPSY2012-69,RECONF2012-74
An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths

Kazuo YAMANE,  Kunihiro FUJIYOSHI,  

[Date]2013/1/9
[Paper #]VLD2012-121,CPSY2012-70,RECONF2012-75
Alliance EDAツールセットとディープサブミクロンプロセス対応λルールベースセルライブラリによるRohmO.18μmチップ試作検証配置配線ツールの試行(物理設計, FPGA応用及び一般)

Tatsuya HOSOKAWA,  Naohiko SHIMIZU,  

[Date]2013/1/9
[Paper #]VLD2012-122,CPSY2012-71,RECONF2012-76
An Accelerator with minimal data transferring using ring connections

He GUAN,  Jun YAO,  Yasuhiko NAKASHIMA,  

[Date]2013/1/9
[Paper #]VLD2012-123,CPSY2012-72,RECONF2012-77
Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance

Takumi ISHIDA,  Daiki YAMAZAKI,  Masakazu TANIGUCHI,  Kazutoshi SUITOU,  Hiroki MATSUTANI,  Nobuyuki YAMASAKI,  

[Date]2013/1/9
[Paper #]VLD2012-124,CPSY2012-73,RECONF2012-78
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