Information and Systems-Computer Systems(Date:2011/03/11)

Presentation
表紙

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[Date]2011/3/11
[Paper #]
目次

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[Date]2011/3/11
[Paper #]
Examination of network fault detection method by use of AFM

Isao Shimokawa,  Toshiaki Tarui,  Hiroki Miyamoto,  Tomohiro Baba,  

[Date]2011/3/11
[Paper #]CPSY2010-71,DC2010-70
Diagnosis for Automotive Electronic Control System : Extraction of Singular Relation from CAN data with WPMax-SAT

Shuichi SATO,  Takuro KUTSUNA,  Naoya CHUJO,  Noriyoshi SANO,  

[Date]2011/3/11
[Paper #]CPSY2010-72,DC2010-71
Development of a Network Recorder for High-Speed Real-Time Data Acquisition and Packet Capture

Kenji TODA,  Mamoru SEKIYAMA,  

[Date]2011/3/11
[Paper #]CPSY2010-73,DC2010-72
Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits

Nobutaka KITO,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2011/3/11
[Paper #]CPSY2010-74,DC2010-73
Design Method of Easily Testable Parallel Adders under Delay Constraints

Shinichi FUJII,  Naofumi TAKAGI,  

[Date]2011/3/11
[Paper #]CPSY2010-75,DC2010-74
Virtual HILS : Efficient software validation by entire system virtualization

Yasuhiro ITO,  Yasuo SUGURE,  Shigeru OHO,  

[Date]2011/3/11
[Paper #]CPSY2010-76,DC2010-75
Performance Evaluation of High Performance Linpack on a Cell/B.E. Cluster with Heterogeneous Interconnect

Ryota NISHIDA,  Tetsuya NAKAHAMA,  Toshiaki KAMATA,  Yuri NISHIKAWA,  Hideharu AMANO,  

[Date]2011/3/11
[Paper #]CPSY2010-77,DC2010-76
Implementation and evaluation of Mere senne Twister with massive-parallel SIMD processing

Youhei MOCHIZUKI,  Naoyuki YOSHIDA,  Naoki MATSUMOTO,  Yuma MURAKAMI,  Takeshi KUMAKI,  Takeshi FUJINO,  

[Date]2011/3/11
[Paper #]CPSY2010-78,DC2010-77
A study on parallel cryptographic processing with ultra-compact single-board computer

Takeshi KUMAKI,  Yuichiro KUROKAWA,  Takeshi FUJINO,  

[Date]2011/3/11
[Paper #]CPSY2010-79,DC2010-78
Parallel C code generation from Simulink models

Takahiro KUMURA,  Masato EDAHIRO,  Yuichi NAKAMURA,  Nagisa ISHIURA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2011/3/11
[Paper #]CPSY2010-80,DC2010-79
An Architecture for Low-Latency Anonymizing Mechanism

Junichi SAWADA,  Koichi INOUE,  Hiroaki NISHI,  

[Date]2011/3/11
[Paper #]CPSY2010-81,DC2010-80
A Cache Control Method for Optimizing Receive Queue with Cache Injection

Ryota MIBU,  Tomoyoshi SUGAWARA,  

[Date]2011/3/11
[Paper #]CPSY2010-82,DC2010-81
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[Date]2011/3/11
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