Information and Systems-Computer Systems(Date:2009/04/14)

Presentation
表紙

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[Date]2009/4/14
[Paper #]
目次

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[Date]2009/4/14
[Paper #]
Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults

Hideo KOHINATA,  Kohei MARUMOTO,  Masayuki ARAI,  Satoshi FUKUMOTO,  

[Date]2009/4/14
[Paper #]CPSY2009-1,DC2009-1
A Development Process with A Model Checking Criterion

Michitaka INUI,  Nobukazu YOSHIOKA,  

[Date]2009/4/14
[Paper #]CPSY2009-2,DC2009-2
Evaluation of a Metropolis Algorithm for Constructing Unstructured Overlay Networks

Tatsushi TAKAMURA,  Tatsuhiro TSUCHIYA,  Toru KIKUNO,  

[Date]2009/4/14
[Paper #]CPSY2009-3,DC2009-3
A Security Data-Flow Analysis in the Secure Software Development Environment DFITS

Fukutomo NAKANISHI,  Ryotaro HAYASHI,  Hiroyoshi HARUKI,  Yurie FUJIMATSU,  Mikio HASHIMOTO,  

[Date]2009/4/14
[Paper #]CPSY2009-4,DC2009-4
Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units

Motoharu HIRATA,  Masayoshi YOSHIMURA,  Yuusuke MATSUNAGA,  Hiroto YASUURA,  

[Date]2009/4/14
[Paper #]CPSY2009-5,DC2009-5
Evolution and threat of botnet

Toshiaki SUDOH,  

[Date]2009/4/14
[Paper #]CPSY2009-6,DC2009-6
A design of testable response analyzers in built-in self-test

Yuki FUKAZAWA,  Yuki YOSHIKAWA,  Hideyuki ICHIHARA,  Tomoo INOUE,  

[Date]2009/4/14
[Paper #]CPSY2009-7,DC2009-7
Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design

Daisuke KOZUWA,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Date]2009/4/14
[Paper #]CPSY2009-8,DC2009-8
Pulse Propagation Analysis for SER Estimation of Logic Circuits

Shoji HARADA,  Yusuke AKAMINE,  Masayoshi YOSHIMURA,  Yusuke MATSUNAGA,  

[Date]2009/4/14
[Paper #]CPSY2009-9,DC2009-9
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[Date]2009/4/14
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Notice for photocopying

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[Date]2009/4/14
[Paper #]
奥付

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[Date]2009/4/14
[Paper #]