Information and Systems-Computer Systems(Date:2004/11/25)

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[Date]2004/11/25
[Paper #]
目次

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[Date]2004/11/25
[Paper #]
Optically Differential Reconfigurable Gate Array with a Pulse Laser

Mototsugu MIYANO,  Minoru WATANABE,  Fuminori KOBAYASHI,  

[Date]2004/11/25
[Paper #]CPSY2004-32
An Optically Differential Reconfigurable Gate Array VLSI

Takenori SHIKI,  Minoru WATANABE,  Fuminori KOBAYASHI,  

[Date]2004/11/25
[Paper #]CPSY2004-33
Evaluation of reconfiguration circuits for Optically Reconfigurable Gate Arrays

Ryuji FUJIME,  Minoru WATANABE,  Fuminori KOBAYASHI,  

[Date]2004/11/25
[Paper #]CPSY2004-34
A delay reduction technique by applying the Small World Network to RLD Routing Structure

Shinya ABE,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2004/11/25
[Paper #]CPSY2004-35
Design of Fast Wavelet Transform Circuits using Partial Hardware Reconfiguration on PCA

Kae SUZUKI,  Toshiyuki ITOU,  Junji KITAMICHI,  Kenichi KURODA,  

[Date]2004/11/25
[Paper #]CPSY2004-36
The Design and Implementation of The IPsec Accelerator with The Dynamically Reconfigurable Processor

Yohei HASEGAWA,  Shohei ABE,  Kenichiro ANJO,  Toru AWASHIMA,  Hideharu AMANO,  

[Date]2004/11/25
[Paper #]CPSY2004-37
A Dynamic Reconfigurable VLC/D Table for High Performance Multi Standards VLC/D Processor

Tomomi EI,  Yuki KURODA,  Midori ONO,  Osamu TOYAMA,  Noriyuki MINEGISHI,  Masayuki MIYAMA,  Masahiko YOSHIMOTO,  

[Date]2004/11/25
[Paper #]CPSY2004-38
Research of a Vision Chip direct coupled type DCT

Kensuke KAWAJIRI,  Taichi NAGAMOTO,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2004/11/25
[Paper #]CPSY2004-39
Input/Output mechanisms of dynamically reconfigurable processors : Move data or change configuration

Hideharu AMANO,  Shohei ABE,  Katsuaki DEGUCHI,  Yoheii HASEGAWA,  

[Date]2004/11/25
[Paper #]CPSY2004-40
An implementation of Dynamic System Optimization Technology, SysteMorph : Implementaion of Dynamic Trace-Based Software Pipelining

Yousuke FUJII,  Makoto YOSHIDA,  Kazuaki MURAKAMI,  

[Date]2004/11/25
[Paper #]CPSY2004-41
Preliminary Performance Evaluation of Dynamic/Adaptive/System Level Optimization Technology, SysteMorph

Kazuhito ESHIMA,  Norifumi YOSHIMATSU,  Takeshi SOGA,  Kazuaki MURAKAMI,  

[Date]2004/11/25
[Paper #]CPSY2004-42
FPGA Implementation and Evaluation of Remote Logic Analyzer IP

Seiji IKEDA,  Kazuo NAGATA,  Hidetomo SHIBAMURA,  Morihiro KUGA,  Toshinori SUEYOSHI,  

[Date]2004/11/25
[Paper #]CPSY2004-43
A Method to Reduce Acknowledgement Overhead of a S-DSM System

Kenji KISE,  Hiroshi TANABE,  Tadayuki OHNO,  Takahiro KATAGIRI,  Hiroki HONDA,  Toshitsugu YUBA,  

[Date]2004/11/25
[Paper #]CPSY2004-44
Development of 4x4 Inverse Matrix Arithmetic Circuit Using Verilog-HDL

Yoshio WADA,  

[Date]2004/11/25
[Paper #]CPSY2004-45
NES on FPGA

Hirokazu SAKAMOTO,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2004/11/25
[Paper #]CPSY2004-46
A study of Non-Raster type Display

Kouichi NAKAO,  Taichi NAGAMOTO,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2004/11/25
[Paper #]CPSY2004-47
Application of Reconfigurable Logics to Image Processing

Teruo TAMAMA,  Tomohiko SAITO,  

[Date]2004/11/25
[Paper #]CPSY2004-48
Evaluation of Object-Recognition Processing with a Reconfigurable System

Hiroshi KADOTA,  Akiyoshi WAKATANI,  

[Date]2004/11/25
[Paper #]CPSY2004-49
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