Information and Systems-Computer Systems(Date:2003/01/22)

Presentation
表紙

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[Date]2003/1/22
[Paper #]
目次

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[Date]2003/1/22
[Paper #]
Asynchronous Multipliers Based on Multi-Wire 2-Phase Data Representation

Ryo NISHINO,  Koki ABE,  

[Date]2003/1/22
[Paper #]CPSY2002-83
A Fast Redundant Binary Multiplier Excluding the Intermediate Sum Operation of Redundant Binary Adders

Tsunetomo NAKAZATO,  Hiroyuki SHIMAJIRI,  Takeo YOSHIDA,  

[Date]2003/1/22
[Paper #]CPSY2002-84
Architecture of Binary Floating-point Adder Using Signed-Digit Number Arithmetic

Junichi HOSOKAWA,  Shugang WEI,  

[Date]2003/1/22
[Paper #]CPSY2002-85
On-line Arbitrary Precision Arithmetic Using Gray Code

Akihiro YONEMOTO,  Takashi HISAKADO,  Masanori GOTO,  Kohshi OKUMURA,  

[Date]2003/1/22
[Paper #]CPSY2002-86
A DSP with Dedicated Functional Units for MPEG-4 Core Profile Encoding

Takeshi ISHIMOTO,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/1/22
[Paper #]CPSY2002-87
A Processor Core Synthesis System Based on Response Time of Hardware IPs

Shunitsu KOHARA,  Hiroki TAGAWA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/1/22
[Paper #]CPSY2002-88
A Hard ware/Soft ware Partitioning Algorithm for Micro Processors Based on Response Time of Hardware IPs

Hiroki TAGAWA,  Shunitsu KOHARA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/1/22
[Paper #]CPSY2002-89
Initial Placement Method using Neural Networks in 3-D VLSI

Takahiro MASAKI,  Kenji SEO,  Michiroh OHMURA,  

[Date]2003/1/22
[Paper #]CPSY2002-90
Solving the Maximum Clique Problem Using FPGAs with Instance-Specific Information

Tomoyuki FUJIWARA,  Shinichi WAKABAYASHI,  

[Date]2003/1/22
[Paper #]CPSY2002-91
Estimating Equivalent Gate Input Waveform for Static Timing Analysis : Coping with waveform distortion due to VDSM processes)

ADA Yuji YAM,  Masanori HASHIMOTO,  Hidetoshi ONODERA,  

[Date]2003/1/22
[Paper #]CPSY2002-92
Design of a Cell Simulation System with FPGA

Yasunori OSANA,  Tomonori FUKUSHIMA,  Hideharu AMANO,  

[Date]2003/1/22
[Paper #]CPSY2002-93
FPGAを用いた高速量子計算エミュレータ(FPGAとその応用及び一般)

Masafumi ONOUCHI,  Kosuke SAITO,  Minoru FUJISHIMA,  Koichiro HOH,  

[Date]2003/1/22
[Paper #]CPSY2002-94
Implementation of Discrete Wavelet Transform on DRP

Katsuaki DEGUCHI,  Yutaka YAMADA,  Hideharu AMANO,  

[Date]2003/1/22
[Paper #]CPSY2002-95
Applying FPGA to Sound Separation by Direction-Pass Filter

Noriaki SUZUKI,  Kazuhiro NAKADAI,  Hideharu AMANO,  Hiroshi OKUNO,  Hiroaki KITANO,  

[Date]2003/1/22
[Paper #]CPSY2002-96
Implementation of Vorbis codec using Configurable Processor

Yukinori YAMANE,  Keishi SAKANUSHI,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2003/1/22
[Paper #]CPSY2002-97
Proposal for USB2.0/1.1 Function Modeling System : an Application of FPGA to the USE Emulation System

Yoshihiro SHIMIZU,  

[Date]2003/1/22
[Paper #]CPSY2002-98
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