Information and Systems-Computer Systems(Date:2002/01/17)

Presentation
表紙

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[Date]2002/1/17
[Paper #]
目次

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[Date]2002/1/17
[Paper #]
Testbed System for Reconfigurable Coprocessing Systems

Yuusuke KAZU,  Takanori HAYASHIDA,  Kazuaki MURAKAMI,  

[Date]2002/1/17
[Paper #]VLD2001-132, CPSY2001-91
PCI Interface by FPGA of Hardware and Software heterogeneous system : The format of Technical Report

Yusuke SHIGA,  Haruki IMANAKA,  Takashi UENO,  Kenji KUDO,  Masatosi SEKINE,  

[Date]2002/1/17
[Paper #]VLD2001-133, CPSY2001-92
Consideration on Tradeoff for Performance : Area of Exponential Function Circuits

Hidenori HATAE,  Koji HASHIMOTO,  Kazuaki MURAKAMI,  

[Date]2002/1/17
[Paper #]VLD2001-134, CPSY2001-93
Size : Position detection algorithm on The Visual Device

Yoshiaki AJIOKA,  Masahiro SHIMADA,  Hideharu AMANO,  

[Date]2002/1/17
[Paper #]VLD2001-135, CPSY2001-94
VLSI Architecture for MPEG-4 Core Profile Video Codec

Takashi NAKAGAWA,  Shinsuke HAMANAKA,  YUNHE Xiao,  Gen FUJITA,  Isao SHIRAKAWA,  

[Date]2002/1/17
[Paper #]VLD2001-136, CPSY2001-95
Implementation of Java Execution Environment for Embedded Systems

Motoki KIMURA,  Morgan Hirosuke MIKI,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]2002/1/17
[Paper #]VLD2001-137, CPSY2001-96
On Delay Minimum Mapping Algorithm for FPGAs Using Boolean Matching

Yusuke MATSUNAGA,  

[Date]2002/1/17
[Paper #]VLD2001-138, CPSY2001-97
An Algorithm of Minimizing AND-EXOR Expressions

Takashi HIRAYAMA,  Yasuaki NISHITANI,  

[Date]2002/1/17
[Paper #]VLD2001-139, CPSY2001-98
Networks Based on Pseudoproduct and its Testability

Ryoji ISHIKAWA,  Tomonori IGARASHI,  Takashi HIRAYAMA,  Kensuke SHIMIZU,  

[Date]2002/1/17
[Paper #]VLD2001-140, CPSY2001-99
A Fast Method to Evaluate Multiple-Output Logic Functions using BDDs

Munehiro MATSUURA,  Yukihiro IGUCHI,  Tsutomu SASAO,  

[Date]2002/1/17
[Paper #]VLD2001-141, CPSY2001-100
Representations of Logic Functions using QRMDDs

Shinobu NAGAYAMA,  Tsutomu SASAO,  Yukihiro IGUCHI,  Munehiro MATSUURA,  

[Date]2002/1/17
[Paper #]VLD2001-142, CPSY2001-101
RTL Optimization and Physical Implementation Methodology in Deep Sub-Micron Design

Satoshi TAKASHIMA,  Kozo KIMURA,  Tokuzo KIYOHARA,  Toshiyuki OCHIAI,  

[Date]2002/1/17
[Paper #]VLD2001-143, CPSY2001-102
A High-Level Power Optimization Algorithm for System VLSIs Based on Area/Delay/Power Estimation

Shinichi NODA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2002/1/17
[Paper #]VLD2001-144, CPSY2001-103
A Compiler Generation Method in The PEAS-III System and Its Evaluation

Shinsuke KOBAYASHI,  Kentaro MITA,  Yoshinori TAKEUCHI,  Masaharu IMAI,  

[Date]2002/1/17
[Paper #]VLD2001-145, CPSY2001-104
[OTHERS]

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[Date]2002/1/17
[Paper #]