Information and Systems-Computer Systems(Date:2001/11/22)

Presentation
表紙

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[Date]2001/11/22
[Paper #]
目次

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[Date]2001/11/22
[Paper #]
A Leak Energy Reduction Technique for Deep Submicron Cache Memories

Tohru ISHIHARA,  Kunihiro ASADA,  

[Date]2001/11/22
[Paper #]CPSY2001-61
Crosstalk Noise Optimization by Post-Layout Transistor Sizing

Masanori HASHIMOTO,  Masao TAKAHASHI,  Hidetoshi ONODERA,  

[Date]2001/11/22
[Paper #]CPSY2001-62
Bit-slice Extraction of Arithmetic Circuits for Layout Design

Yushi OGAWA,  Kazuyoshi TAKAGI,  Naofumi TAKAGI,  

[Date]2001/11/22
[Paper #]CPSY2001-63
A Hierarchical Buffer Block Planning Method for ULSI Floorplanning

Masakazu OHSAKO,  Shin'ichi WAKABAYASHI,  Tetsushi KOIDE,  

[Date]2001/11/22
[Paper #]CPSY2001-64
A Timing-Driven Standard-Cell Placement Method Based on Cell-Clustering and the New Placement Model

Nobuyuki IWAUCHI,  Shin'ichi WAKABAYASHI,  Tetsushi KOIDE,  

[Date]2001/11/22
[Paper #]CPSY2001-65
The translation from SystemC to Verilog-HDL keeping the character of signal

Fumiaki NAGAO,  

[Date]2001/11/22
[Paper #]CPSY2001-66
CAD Simulation Technology in System LSI Design

Akitoshi MATSUDA,  

[Date]2001/11/22
[Paper #]CPSY2001-67
A Pipelining Architecture for A High Speed and Low Power CMOS Logic Technology ASDL and Its Evaluation

Mikio YAGI,  Masao MORIMOTO,  Kazuo TAKI,  Kiyoshi KITAMURA,  

[Date]2001/11/22
[Paper #]CPSY2001-68
A Low Power Cache Memory Architecture based on Tag Compare Reuse

Koji Inoue,  Moshnyaga G. Vasily,  Kazuaki Murakami,  

[Date]2001/11/22
[Paper #]CPSY2001-69
Reducing power consumption of Video memory through data compression

Mizuka Fukagawa,  Koji Inoue,  Vasily G. Moshnyaga,  

[Date]2001/11/22
[Paper #]CPSY2001-70
Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply

Hiroshi Tsuji,  Koji Inoue,  Vasily G. Moshnyaga,  

[Date]2001/11/22
[Paper #]CPSY2001-71
Logic Synthesis for PLA with 2-input Logic Elements

Hiroaki YOSHIDA,  Hiroaki YAMAOKA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2001/11/22
[Paper #]CPSY2001-72
Multi-Cycle Path Analysis for Large Sequential Circuits

Hiroyuki Higuchi,  

[Date]2001/11/22
[Paper #]CPSY2001-73
On Identifying Don't-Care Inputs of Test Patterns for Logic Circuits

Kohei MIYASE,  Seiji KAJIHARA,  

[Date]2001/11/22
[Paper #]CPSY2001-74
[OTHERS]

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[Date]2001/11/22
[Paper #]