Information and Systems-Computer Systems(Date:2001/01/05)

Presentation
表紙

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[Date]2001/1/5
[Paper #]
目次

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[Date]2001/1/5
[Paper #]
A Discrete Cosine Transform Circuit with Dynamically Reconfigurabie Digit-Serial Computation

Kazuhito Ito,  

[Date]2001/1/5
[Paper #]VLD2000-117,CPSY2000-72
Dynmaic Reconfigurable Network Node

Takahiro Murooka,  Toshiaki Miyazaki,  

[Date]2001/1/5
[Paper #]VLD2000-118,CPSY2000-73
A Resource Binding Algorithm Basedon Computation Time Estimation Using Heurisitic Method and Branch-and-bound Method

Hirosshi NAKAMURA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2001/1/5
[Paper #]VLD2000-119,CPSY2000-74
Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment

Seiichieo Ishijima,  Atsushi Takahashi,  

[Date]2001/1/5
[Paper #]VLD2000-120,CPSY2000-75
On a Technique to Eliminate False-Paths for the Statistical Static Timing Analysis

Shuji Tsukiyama,  Masakazu Tanaka,  Masahiro Fukui,  

[Date]2001/1/5
[Paper #]VLD2000-121,CPSY2000-76
Super-cell Design Based on Statically Substrate-biased Domino CMOS Circuit I : Cell Layout Architecture with Continuously Variable Transistor Width

Toshiro Akino,  Yoshinobu Sakai,  Hironori Takahashi,  

[Date]2001/1/5
[Paper #]VLD2000-122,CPSY2000-77
A Hierarchical Parallel and Distribated placer on a PC Cluster by using Voyager

Norihisa WATANUKI,  Yoichi SHIRAISHI,  

[Date]2001/1/5
[Paper #]VLD2000-123,CPSY2000-78
AnImplementaion of Parallel Distributed Device Model Evaluation on Simulation

Tsuyoshi Suzuki,  Hiroyuki Yagi,  Ryo Dang,  

[Date]2001/1/5
[Paper #]VLD2000-124,CPSY2000-79
Estimation for the performance of the circuit calculates diode model parameter

Hiroshi Kawakami,  Tsuyoshi Suzuki,  Ryo Dang,  

[Date]2001/1/5
[Paper #]VLD2000-125,CPSY2000-80
Design Optimization Method Using Digit Serial Operation for DSP Systems

Yoshiharu Watanabe,  Yoshinori Takeuchi,  Akira Kitajima,  Masaharu Imai,  

[Date]2001/1/5
[Paper #]VJD2000-126,CPSY2000-81
[OTHERS]

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[Date]2001/1/5
[Paper #]