Information and Systems-Computer Systems(Date:2000/01/11)

Presentation
表紙

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[Date]2000/1/11
[Paper #]
目次

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[Date]2000/1/11
[Paper #]
Multiplier on FPGAs with 3bit Compaction and Redundant Binary Representation

Takahiro MIOMO,  Koichi YASUOKA,  Masanori KANAZAWA,  

[Date]2000/1/11
[Paper #]VLD99-87,CPSY99-96
VLSI Implementation and Performance Evaluation of URR Floating-Point Multiplier

Takeshi KATSU,  Koki ABE,  Hozumi HAMADA,  

[Date]2000/1/11
[Paper #]VLD99-88,CPSY99-97
A subtract-and-shift cube rooting circuit

Naofumi TAKAGI,  Toshiaki MINAMI,  

[Date]2000/1/11
[Paper #]VLD99-89,CPSY99-98
Lazy Group Sifting for Efficient Symbolic Traversal of Sequential Circuits

Hiroyuki HIGUCHI,  Fabio SOMENZI,  

[Date]2000/1/11
[Paper #]VLD99-90,CPSY99-99
An Algorithm for Generating Generic BDDs

Tetsushi KATAYAMA,  Hiroyuki OCHI,  Takao TSUDA,  

[Date]2000/1/11
[Paper #]VLD99-91,CPSY99-100
Node Codings for Implicit Representation of Binary Decision Diagrams

Hitoshi YAMAUCHI,  Hiromitsu TAKAHASHI,  

[Date]2000/1/11
[Paper #]VLD99-92,CPSY99-101
An Efficient Algorithm to Extract An Optimal Sub-Circuit by the Minimum Cut

Kengo AZEGAMI,  Atsushi TAKAHASHI,  Yoji KAJITANI,  

[Date]2000/1/11
[Paper #]VLD99-93,CPSY99-102
Constrained Via Minimization Algorithm PNLA based on Partitioning a Set of Nets for Layer Assignment

Toshihiro KOBAYASHI,  Toshimasa WATANABE,  

[Date]2000/1/11
[Paper #]VLD99-94,CPSY99-103
Heuristic Algorithms for Routing Nonplanar Connections through Areas under Elements in Printed Wiring Board Design

Daisuke TAKAFUJI,  Sinpei SUMIKAWA,  Toshimasa WATANABE,  

[Date]2000/1/11
[Paper #]VLD99-95,CPSY99-104
Development of Bit-Serial FPGA System

Tsuyoshi ISSHIKI,  Akihisa OHTA,  Hiroaki KUNIEDA,  

[Date]2000/1/11
[Paper #]VLD99-96,CPSY99-105
[OTHERS]

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[Date]2000/1/11
[Paper #]