Information and Systems-Computer Systems(Date:1998/10/16)

Presentation
表紙

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[Date]1998/10/16
[Paper #]
目次

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[Date]1998/10/16
[Paper #]
Bus Architecture for 600-MHz 4.5-Mb DDR SRAM

Osamu Hirabayashi,  Azuma Suzuki,  Hiroshi Hatada,  Atsushi Kawasumi,  Yasuhisa Takeyama,  Takahiro Hamano,  Nobuaki Otsuka,  

[Date]1998/10/16
[Paper #]DSP98-012,ICD98-189,CPSY98-104
Non-Precharged Bit-Line Sensing Scheme for High-Speed Low-Power DRAMs

Takahiro Yokoyama,  Yoshiharu Kato,  Nobuyoshi Nakaya,  Teruaki Maeda,  Mitsuhiro Higashiho,  Yasuhisa Sugo,  Fumio Baba,  Tooru Miyabo,  Satoru Saito,  Yoshihiro Takemae,  

[Date]1998/10/16
[Paper #]DSP98-103,ICD98-190,CPSY98-105
Reduction of DRAM Row Cycle Time by Using Temporal buffer Scheme

Shigetoshi Wakayama,  Kohtaroh Gotoh,  Miyoshi Saito,  Junji Ogawa,  Hisakatsu Araki,  Tsu-shing Cheung,  Hirotaka Tamura,  Takeshi Imamura,  

[Date]1998/10/16
[Paper #]DSP98-104,ICD98-191,CPSY98-106
A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme

Isao FUKUSHI,  Ryuhei SASAGAWA,  Makoto HAMAMINATO,  Tetsuo IZAWA,  Shoichiro KAWASHIMA,  

[Date]1998/10/16
[Paper #]DSP98-105,ICD98-192,CPSY98-107
A 256 Byte Embedded FeRAM Macro Cell for a Smart Card Microcontroller

Tohru Miwa,  Junichi Yamada,  Yuji Okamoto,  Hiroki Koike,  Hideo Toyoshima,  Hiromitsu Hada,  Yoshihiro Hayashi,  Hiroaki Okizaki,  Yoichi Miyasaka,  Takemitsu Kunio,  Hidenobu Miyamoto,  Hideki Gomi,  Hiroshi Kitajima,  

[Date]1998/10/16
[Paper #]DSP98-106,ICD98-193,CPSY98-108
High-speed SRAM Macros using a Configurable Organization Technique with an Automatic Timing Adjuster

Kazumasa Ando,  Keiichi Higeta,  Yasuhiro Fujimura,  Kazutaka Mori,  Michiaki Nakayama,  Hiroaki Nambu,  Kazuhisa Miyamoto,  Kunihiko Yamaguchi,  

[Date]1998/10/16
[Paper #]DSP98-107,ICD98-194,CPSY98-109
A Pipeline-Operating, Fast Row-Cycle Memory FCRAM in High-Speed DRAM ARchitecture Movement

Masao Taguchi,  

[Date]1998/10/16
[Paper #]DSP98-108,ICD98-195,CPSY98-110
Considerations on Memory Architectures for FLASH Main Memory

Koji KAI,  Akihiko INOUE,  Hiroto YASUURA,  

[Date]1998/10/16
[Paper #]DSP98-109,ICD98-196,CPSY98-111
An Affine Transformer for Rectangular Video Image using Two Identical Functional Blocks.

Yoshimichi Takahara,  Hiroto Kagotani,  Yoichiro Sato,  Takuji Okamoto,  

[Date]1998/10/16
[Paper #]DSP98-110,ICD98-197,CPSY98-112
Proposal of User Interfaces for Petri Net Controller and Modeling Language for factory Automation Systems

Yuji TAKEDA,  Hideki MURAKOSHI,  Noboru FUNAKUBO,  Yasunori DOHI,  

[Date]1998/10/16
[Paper #]DSP98-111,ICD98-198,CPSY98-113
Conditions for Reducing the Realization Dimension of Two-Dimensional Digital Filters

Atsushi KAWAKAMI,  

[Date]1998/10/16
[Paper #]DSP98-112,ICD98-199,CPSY98-114
Blind System Identification Using RLS Method Based on Second-Order Statistics

Takashi Kimura,  Hideaki Sasaki,  Mirai Oshiro,  Hiroshi Ochi,  

[Date]1998/10/16
[Paper #]DSP98-113,ICD98-200,CPSY98-115
Higher Resolution of Digital Images Based on Laplacian Pyramid Representation

Yasumasa TAKAHASHI,  Daisuke SEKIWA,  Akira TAGUCHI,  

[Date]1998/10/16
[Paper #]DSP98-114,ICD98-201,CPSY98-116
A Method of Inserting Binary Data into MPEG Bitstreams

Ayuko TAKAGI,  Hiroyuki KOBAYASHI,  Yoshihiro NOGUCHI,  Hitoshi KIYA,  

[Date]1998/10/16
[Paper #]DSP98-115,ICD98-202,CPSY98-117
Formula Identification Using Genetic Algorithms

Hideto Nishikado,  Kouichi Shiba,  Hironori Yamauchi,  Hiroshi Yasukawa,  

[Date]1998/10/16
[Paper #]DSP98-116,ICD98-203,CPSY98-118
[OTHERS]

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[Date]1998/10/16
[Paper #]