Information and Systems-Computer Systems(Date:1998/09/22)

Presentation
表紙

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[Date]1998/9/22
[Paper #]
目次

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[Date]1998/9/22
[Paper #]
Implementation of a GA Engine without Pipeline Stalls

Osamu Kitaura,  Hiroyuki Sugiura,  Takamitsu Kawai,  Hideki Ando,  Toshio Shimada,  

[Date]1998/9/22
[Paper #]CPSY98-81
A VLSI Architecture for Fractal Image Coding

Shinhaeng Lee,  Hirotomo Aso,  

[Date]1998/9/22
[Paper #]CPSY98-82
A Method for Implementing Fractal Image Compression on Reconfigurable Architecture

Akihiro MATSUURA,  Hidehisa NAGANO,  Akira NAGOYA,  

[Date]1998/9/22
[Paper #]CPSY98-83
A Hardware Implementation of Electromagnetic Particle Simulation with Reconfigurable Hardware

Yoshikatsu Ueda,  Yukihiro Nakamura,  Tsunemichi Shiozawa,  Takayuki Suyama,  

[Date]1998/9/22
[Paper #]CPSY98-84
A Hardware/Software Cosynthesis System for Processors with Content Addressable Memory

Makoto TERAJIMA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]1998/9/22
[Paper #]CPSY98-85
Concurrent Design Environment for System LSIs : A Single-chip MPEG-2 MP@ML Video Encoder LSI

Katsuyuki OCHIAI,  Hiroe IWASAKI,  Jiro NAGANUMA,  Makoto ENDO,  

[Date]1998/9/22
[Paper #]CPSY98-86
Logic synthesis of finely pipelined asynchronous datapaths using DGVSL cells

Masashi Imai,  Hiroshi Nakamura,  Takashi Nanya,  

[Date]1998/9/22
[Paper #]CPSY98-87
A Method for Improving Combinational Circuits using Simple Disjunctive Decompositions

Hiroshi SAWADA,  Shigeru YAMASHITA,  Akira NAGOYA,  

[Date]1998/9/22
[Paper #]CPSY98-88
A Fast Constructive Method for Hypergraph Partitioning

Yoko Kamidoi,  Shin'ichi Wakabayashi,  Noriyoshi Yoshida,  

[Date]1998/9/22
[Paper #]CPSY98-89
A proposal of a three-stage greedy neural-network algorithm for FPGA routing problems

SHINJI EGAWA,  EIJI KURODA,  JUNJI KITAMICHI,  NOBUO FUNABIKI,  

[Date]1998/9/22
[Paper #]CPSY98-90
[OTHERS]

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[Date]1998/9/22
[Paper #]