Information and Systems-Computer Systems(Date:1998/04/24)

Presentation
表紙

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[Date]1998/4/24
[Paper #]
目次

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[Date]1998/4/24
[Paper #]
A Low Power MPEG4 Video Codec with Variable Supply-Volgata Scheme

Tsuyoshi Nishikawa,  Masafumi Takahashi,  Mototsugu Hamada,  Hideho Arakida,  Yoshiroh Tsuboi,  Tetsuya Fujita,  Fumitoshi Hatori,  Shinji Mita,  Kojiro Suzuki,  Masakazu Suzuki,  Fumio Yoshida,  Atsushi Asano,  Hiroshi Momose,  Tadahiro Kuroda,  Akihiko Chiba,  Toshihiro Terazawa,  Fumihiko Sano,  Yoshinori Watanabe,  Tohru Furuyama,  

[Date]1998/4/24
[Paper #]
1.2W2.16GOPS/720MFLOPS Embedded Superscalar Microprocessor for Multimedia Applications

Atsuhiro Suga,  Hajime Kubosawa,  Hiromasa Takahashi,  Satoshi Ando,  Yoshimi Asada,  Akira Asato,  Michihide Kimura,  Naoshi Higaki,  Hideo Miyake,  Tomio Sato,  Hideaki Anbutsu,  Toshitaka Tsuda,  

[Date]1998/4/24
[Paper #]
Design of a 200MHz 1.2W 1.4GFLOPS Processor with Graphic Floating-point Extension

Osamu NISHI,  Fumio ARAKAWA,  Koichiro ISHIBASHI,  Sadaki NAKANO,  Takanori SHIMURA,  Kei SUZUKI,  Mitsugu TACHIBANA,  Yonetaro TOTSUKA,  Takanobu TSUNODA,  Kunio UCHIYAMA,  Tetsuya YAMADA,  Toshihiro HATTORI,  Hideo MAEJIMA,  Norio NAKAGAWA,  Susumu NARITA,  Mitsuho SEKI,  Yasuhisa SHIMAZAKI,  Ryuuichi SATOMURA,  Tomoya TAKASUGA,  Atsushi HASEGAWA,  

[Date]1998/4/24
[Paper #]
A Design of the Java Virtual Machine Using VHDL and Its Implementation on an FPGA Device

Hiroaki Fujimoto,  Koji Kawashima,  Kenji Fujisawa,  Yoshihisa Desaki,  Kazuhiko Iwasaki,  

[Date]1998/4/24
[Paper #]
Accelerating Concurrent Fault Simulation by Emptiness Checking of Fault Lists and Analysis of Reconvergence

Yukio ISHIBASHI,  Masahiro NAGAMATSU,  Torao YANARU,  

[Date]1998/4/24
[Paper #]
An Implemention and Evaluation of the FTAG model for fault torelant software

Masumi TOYOSHIMA,  Masato SUZUKI,  Takuya KATAYAMA,  

[Date]1998/4/24
[Paper #]
Design of Pseudo Asynchronous Microprocessor with Completion Detection Pipelined Adder

Yoshinori SATO,  Ruo-Tong ZHENG,  Kunihiro ASADA,  

[Date]1998/4/24
[Paper #]
Performance Evaluation for Asynchronous Pipeline Structure

Motokazu OZAWA,  Akihiro TAKAMURA,  Yoichiro UENO,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]1998/4/24
[Paper #]
Asynchronous Cascade ALU Architecture

Yoichiro UENO,  Izumi Fukasaku,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]1998/4/24
[Paper #]
Dynamically Reconfigurable VLSI Processor and its Layout Method

Hiroshi Nakada,  Kiyoshi Oguri,  Norbert Imlig,  Thunemichi Shiozawa,  Minoru Inamori,  

[Date]1998/4/24
[Paper #]
PPRAM-MOE : A Processing Node LSI of The Molecular Orbital Calculation Engine (MOE)

Shinjiro Inabata,  So Yamada,  Taku Osawa,  Kouichi Okino,  Hiroto Tomita,  Kouji Hashimoto,  Kiyoshi Hayakawa,  Nobuaki Miyazaki,  Kazuaki Murakami,  

[Date]1998/4/24
[Paper #]
Bus Instruction Set Computer BISC-1

Kenichi Maruko,  Yukihiko Yamashita,  

[Date]1998/4/24
[Paper #]
Fetch System of Very Large Data Path Processor

Tomohiro Nakamura,  Kenji Kise,  Hidenori Tsuji,  Yuichiro Ajima,  Makoto Takamine,  Hidehiko Tanaka,  

[Date]1998/4/24
[Paper #]
System Control LSI Reflecting Data Directly on Main Memory for Highly Reliable Controller

Y Sato,  S Tanaka,  S Yoshida,  S Ohtsuji,  T Hotta,  H Tanaka,  

[Date]1998/4/24
[Paper #]
Dynamically Variable Line-Size Caches Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs

Koji Inoue,  Koji Kai,  Kazuaki Murakami,  

[Date]1998/4/24
[Paper #]
Software Controled Cache for Multi-grain Parallel Processing

Katsuto Sakamoto,  Takashi Fujiwara,  Takahiro Kawaguchi,  Keisuke Iwai,  Tomohiro Morimura,  Hideharu Amano,  

[Date]1998/4/24
[Paper #]
[OTHERS]

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[Date]1998/4/24
[Paper #]