IEICE Technical Committee

Information and Systems-Computer Systems(Date:1997/10/29)

Presentation

表紙

[Date]1997/10/29
[Paper #]

On VLSI Decompositions for deBruijn Graphs

Satoshi Imai, Toshinori Yamada, Shuichi Ueno,

[Date]1997/10/29
[Paper #]CPSY97-68

Clock Routing Driven Placement in Semi-Synchronous Circuits

Wataru Takahashi, Atsushi Takahashi, Yoji Kajitani,

[Date]1997/10/29
[Paper #]CPSY97-69

Cost-Radius Balanced Plane Steiner Trees

Hideki Mitsubayashi, Atsushi Takahashi, Yoji Kajitani,

[Date]1997/10/29
[Paper #]CPSY97-70

A Routing System for Leaf Cell Design

Noriko Shinomiya, Yasuo Nishigaki, Masahiro Fukui,

[Date]1997/10/29
[Paper #]CPSY97-71

Deep-submicron Gate Array Design Example

Sigenori Horiuchi, Yasuyuki Furuta, Goro Suzuki,

[Date]1997/10/29
[Paper #]CPSY97-72

Delay Calculation Method with Precomputed table for Pass-transistor Logic

Bu-Yeol LEE, Kenzo KONISHI, Kazuo TAKI,

[Date]1997/10/29
[Paper #]CPSY97-73

The transmission line noise automatic decision system of the high speed circuit board

Hideaki Sonoda,

[Date]1997/10/29
[Paper #]CPSY97-74

The establishment of the whole chip function verification method for Mixed-Signal LSI

Hiroshi Uematsu, Yousuke Motono, Masato Iwabuchi, Katsuhiro Furukawa, Takashi Yamazaki,

[Date]1997/10/29
[Paper #]CPSY97-75

A Fast Parallel-Fault Simulation Algorithm Using a CAM-Based Hardware Engine

Seiichiro FUKUYAMA, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI,

[Date]1997/10/29
[Paper #]CPSY97-76

Power Optimization with Variable Voltage Processor

Tohru ISHIHARA, Hiroto YASUURA,

[Date]1997/10/29
[Paper #]CPSY97-77

An Educational Course on Fully Interlocked Pipeline CISC/RISC Design : 2nd report of Microcomputer Design Educational Environment City-1

Ryuichi TAKAHASHI, Noriyoshi YOSHIDA,

[Date]1997/10/29
[Paper #]CPSY97-78

Minimization of FPGA Circuits Utilizing Block Integration

Takenori Kouda, Yahiko Kambayashi,

[Date]1997/10/29
[Paper #]CPSY97-79

A dedicated CAD system for telecom-FPGA having rich routing resources

Takahiro Murooka, Atsushi Takahara, Akihiro Tsutsui, Toshiaki Miyazaki,

[Date]1997/10/29
[Paper #]CPSY97-80

Full Custom Design for Bit Serial FPGA

Akihisa Ohta, Takenobu Shimizugashira, Imanuddin Amril, Tsuyoshi Isshiki, Hiroaki Kunieda,

[Date]1997/10/29
[Paper #]CPSY97-81

High-Performance Bit-Serial Pipeline Datapath Synthesis

Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Hiroaki Kunieda,

[Date]1997/10/29
[Paper #]CPSY97-82

Transduction Method with Pattern-based Transformations

M. Kumazawa, S. Sawada, Y. Kambayashi,

[Date]1997/10/29
[Paper #]CPSY97-83

Efficient Simple Disjunctive Decompositions by Detecting Symmetric Variables with Application to Multi-level Logic Synthesis

Hiroshi SAWADA, Shigeru YAMASHITA, Akira NAGOYA,

[Date]1997/10/29
[Paper #]CPSY97-84

Semantic Analysis of VHDL-AMS by Attribute Grammar

Takeshi Sasaki, Hisashi Sasaki, Kazunori Mizushima,

[Date]1997/10/29
[Paper #]CPSY97-85