Information and Systems-Computer Systems(Date:1997/08/19)

Presentation
表紙

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[Date]1997/8/19
[Paper #]
目次

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[Date]1997/8/19
[Paper #]
[CATALOG]

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[Date]1997/8/19
[Paper #]
Implementation and Evaluation of WS cluster JUMP-1/3-SL

W. Ono,  K. Anjo,  H. Nakajo,  K. Kudoh,  J. Yamamoto,  H. Amano,  

[Date]1997/8/19
[Paper #]CPSY97-36
Subprotocols for Localizing the Coherence Transactions in Regular Computation

Masaru Takesue,  

[Date]1997/8/19
[Paper #]CPSY97-37
Proposition and Evaluation of Hierachical Commitment Algorithm for Permanent Time Stamp Ordering

Kouji Matsuura,  Shin-ya Kobayashi,  

[Date]1997/8/19
[Paper #]CPSY97-38
Evaluation of a Practical Parallel Optimization Algorithm for the Minimum Execution-Time Multiprocessor Scheduling Problem

TAKAO TOBITA,  HIRONORI KASAHARA,  

[Date]1997/8/19
[Paper #]CPSY97-39
A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer

KEIJI KIMURA,  SHIGERU HASHIMOTO,  MAKOTO KOGOU,  WATARU OGATA,  HIRONORI KASAHARA,  

[Date]1997/8/19
[Paper #]CPSY97-40
Parallelizing Emulation Based on Speculative Dataflow Model:A Perspective

Hanpei KOIKE,  Yoshinori YAMAGUCHI,  

[Date]1997/8/19
[Paper #]CPSY97-41
Load balancing with SSS-Server

Shigero SASAKI,  Hiroyuki KAMESAWA,  Takashi MATSUMOTO,  Kei HIRAKI,  

[Date]1997/8/19
[Paper #]CPSY97-42
Performance Evaluation of MIMD Multicomputers by Half-Speed Methodology

Daiki Abe,  Tsutomu Yoshinaga,  Kanemitsu Ootsu,  Takanobu Baba,  

[Date]1997/8/19
[Paper #]CPSY97-43
An Evaluation of Logic Emulation using a Fine-grain Packet-based Processor for a Highly Parallel Computer

Yuetsu KODAMA,  Hirofumi SAKANE,  Yoshinori YAMAGUCHI,  

[Date]1997/8/19
[Paper #]CPSY97-44
HOSMII:a Virtual Hardware System Based on an FPGA Embedded with DRAM

Y. Shibata,  H. Miyazaki,  X.-P Ling,  H. Amano,  

[Date]1997/8/19
[Paper #]CPSY97-45
Multi-processor system for Multi-grain Parallel Processing

Keisuke Iwai,  Takashi Fujiwara,  Tomohiro Morimura,  Hideharu Amano,  Keiji Kimura,  Wataru Ogata,  Hironori Kasahara,  

[Date]1997/8/19
[Paper #]CPSY97-46
The Multi-stage Interconnection Network R-Clos for emulating the hierarchical multi-bus model

T. Morimura,  K. Iwai,  H. Amano,  

[Date]1997/8/19
[Paper #]CPSY97-47
Implementation of a Router Chip for the Massively Parallel Computer RWC-1

Takashi Yokota,  Hiroshi Matsuoka,  Kazuaki Okamoto,  Hideo Hirono,  Shuichi Sakai,  Koji Tasyo,  Toshiyuki Shimizu,  

[Date]1997/8/19
[Paper #]CPSY97-48
An optical interconnection network for WS cluster

Hiroaki Nishi,  Tomohiro Kudoh,  Hideharu Amano,  

[Date]1997/8/19
[Paper #]CPSY97-49
Performance of Memory-Based Communication Facilities Using Fast Ethernet (100BaseTX)

Takashi MATSUMOTO,  Kei HIRAKI,  

[Date]1997/8/19
[Paper #]CPSY97-50
[OTHERS]

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[Date]1997/8/19
[Paper #]