Information and Systems-Computer Systems(Date:1996/01/31)

Presentation
表紙

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[Date]1996/1/31
[Paper #]
目次

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[Date]1996/1/31
[Paper #]
A Trace Driven Simulator for Multiprocessors with Multistage Interconection Network(MIN)

T. Komeda,  T. Kamei,  H. Yasukawa,  T. Hanawa,  T. Terasawa,  H. Amano,  

[Date]1996/1/31
[Paper #]CPSY95-99
The Evaluation of SNAIL with Parallel Benchmark Programs

T. Fujiwara,  Y. Kitoh,  Y. Yamaguchi,  T. Hanawa,  T. Kamei,  T. Komeda,  J. Yamamoto,  H. Amano,  

[Date]1996/1/31
[Paper #]CPSY95-100
Methods of avoiding Deadlocks in the Controller using Petri Net

Eiji Nomura,  Yasunori Dohi,  Hideki Murakoshi,  

[Date]1996/1/31
[Paper #]CPSY95-101
Proposal of The Methodology Modeling for FA Systems and The Improved Petri Net Controller

Yuji TAKEDA,  Hdeki MURAKOSHI,  Yasunori DOHI,  

[Date]1996/1/31
[Paper #]CPSY95-102
Memory Trend of Computer Systems

Michihiro YAMADA,  Masaki KUMANOYA,  

[Date]1996/1/31
[Paper #]CPSY95-103
2D-DFT Fault Tolerant Systolic Array

Tetsuhiro Kubo,  Tomoyuki Ohkawa,  Yasunori Dohi,  

[Date]1996/1/31
[Paper #]CPSY95-104
A file system for continuous media data on disk arrays

Yasuhiro MORI,  Shinji SASAKI,  Manabu MIGITA,  Shinji FURUYA,  Katsuyuki KANEKO,  

[Date]1996/1/31
[Paper #]CPSR95-105
Neural Network Hardware Eliminating Negligible Connections

Noritaka Hoshi,  Shuichi Ichikawa,  Toshio Shimada,  

[Date]1996/1/31
[Paper #]CPSY95-106
A Method to Control Cache Memory Subsystem with Synchronous DRAMs

Toshitaka MIURA,  Yoichi MURAOKA,  

[Date]1996/1/31
[Paper #]CPSY95-107
The structure of Z-Cache and its performance evaluation

Takuya Terasawa,  

[Date]1996/1/31
[Paper #]CPSY95-108
[OTHERS]

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[Date]1996/1/31
[Paper #]