Information and Systems-Computer Systems(Date:1995/04/27)

Presentation
表紙

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[Date]1995/4/27
[Paper #]
目次

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[Date]1995/4/27
[Paper #]
A 0.25μm CMOS 0.9V 100MHz DSP Core

Masanori Izumikawa,  Hiroyuki Igura,  Koichiro Furuta,  Hiroshi Ito,  Hitoshi Wakabayashi,  Ken Nakajima,  Tohru Mogami,  Tadahiko Horiuchi,  Masakazu Yamashina,  

[Date]1995/4/27
[Paper #]
A 150MIPS/W CMOS RISC Processor for PDA Applications

Masato Nagamatsu,  Ken Mabuchi,  Takashi Miyamori,  Hiroaki Murakami,  Yukio Ootaguro,  Harutaka Goto,  Toru Utsumi,  Tatsuo Teruyama,  

[Date]1995/4/27
[Paper #]
A Study of an On-chip Multiprocessor Architecture

Masafumi Takahashi,  Hiroyuki Takano,  Seigo Suzuki,  Haruyuki Tago,  

[Date]1995/4/27
[Paper #]
Performance Evaluation of GHz-Class RISC Pipeline Architecture

Emi Kaneko,  Masafumi Takahashi,  Haruyuki Tago,  

[Date]1995/4/27
[Paper #]
1.5-V Source-Coupled Current-Mode Multiple-Valued Integrated Circuits and Its Application to a High-Speed Pipelined Multiplier

Takahiro Hanyu,  Akira Mochizuki,  Michitaka Kameyama,  

[Date]1995/4/27
[Paper #]
Reconfigurable Parallel VLSI Processor Based on Bit-Serial Architecture and Its Application to Intelligent Integrated Systems

Yoshinori Ueno,  Yoshichika Fujioka,  Michitaka Kameyama,  

[Date]1995/4/27
[Paper #]
A Sparse Memory-Access Neural Network Engine with 96 Parallel Data-Driven Processing Units

Kimihisa Aihara,  Osamu Fujita,  Kuniharu Uchimura,  

[Date]1995/4/27
[Paper #]
Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment

K. Kotani,  T. Shibata,  M. Imai,  T. Ohmi,  

[Date]1995/4/27
[Paper #]
Circuit constraction for Thinning using ν MOS Cellular Automata

Masayuki Ikebe,  Koji Kameishi,  Yoshihito Amemiya,  

[Date]1995/4/27
[Paper #]
Pulse Width Modulation based signal processing circuits and its application for Kohonen Network

Makoto Nagata,  Takahiro Yoneda,  Atsushi Iwata,  

[Date]1995/4/27
[Paper #]
[OTHERS]

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[Date]1995/4/27
[Paper #]